Datasheet > MM54C175J

MM54C175J

更新时间： 2023-01-02 17:12:21

品牌	Logo	应用领域
德州仪器 - TI		输出元件
页数	文件大小	规格书
6页	324K
描述
CMOS SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16, CERAMIC, DIP-16

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MM54C175J 数据手册

February 1988

MM54C175/MM74C175 Quad D Flip-Flop

General Description

The MM54C175/MM74C175 consists of four positive-edge

All inputs are protected from static discharge by diode

clamps to V and GND.

triggered type flip-flops implemented with monolithic

CMOS technology. Both are true and complemented out-

puts from each flip-flop are externally available. All four flip-

flops are controlled by a common clock and a common

clear. Information at the D inputs meeting the set-up time

requirements is transferred to the Q outputs on the positive-

going edge of the clock pulse. The clearing operation, en-

abled by a negative pulse at Clear input, clears all four Q

outputs to logical ‘‘0’’ and Q’s to logical ‘‘1’’.

Features

Wide supply voltage range

Guaranteed noise margin

High noise immunity

3V to 15V

1.0V

0.45 V

(typ.)

Low power TTL compatibility

Fan out of 2

driving 74L

Connection Diagram & Truth Table

Dual-In-Line Package

TL/F/5900–1

Top View

Order Number MM54C175 or MM74C175

Each Flip-Flop

Inputs

Clock

Outputs

Clear

High level

Low level

Irrelevant

Transition from low to high level

No change

1995 National Semiconductor Corporation

TL/F/5900

RRD-B30M105/Printed in U. S. A.

12 3 4 5 6

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