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MM54C00J PDF预览

MM54C00J

更新时间: 2024-11-15 19:57:43
品牌 Logo 应用领域
美国国家半导体 - NSC 输入元件逻辑集成电路
页数 文件大小 规格书
6页 145K
描述
IC TTL/H/L SERIES, QUAD 2-INPUT NAND GATE, CDIP14, CERAMIC, DIP-14, Gate

MM54C00J 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP14,.3Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.31
系列:TTL/H/LJESD-30 代码:R-CDIP-T14
JESD-609代码:e0长度:19.43 mm
负载电容(CL):50 pF逻辑集成电路类型:NAND GATE
最大I(ol):0.00036 A功能数量:4
输入次数:2端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:DIP
封装等效代码:DIP14,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5/15 VProp。Delay @ Nom-Sup:90 ns
传播延迟(tpd):90 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:5.08 mm
子类别:Gates最大供电电压 (Vsup):15 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

MM54C00J 数据手册

 浏览型号MM54C00J的Datasheet PDF文件第2页浏览型号MM54C00J的Datasheet PDF文件第3页浏览型号MM54C00J的Datasheet PDF文件第4页浏览型号MM54C00J的Datasheet PDF文件第5页浏览型号MM54C00J的Datasheet PDF文件第6页 
February 1988  
MM54C00/MM74C00 Quad 2-Input NAND Gate  
MM54C02/MM74C02 Quad 2-Input NOR Gate  
MM54C04/MM74C04 Hex Inverter  
MM54C10/MM74C10 Triple 3-Input NAND Gate  
MM54C20/MM74C20 Dual 4-Input NAND Gate  
General Description  
Features  
Y
Wide supply voltage range  
3V to 15V  
1V  
These logic gates employ complementary MOS (CMOS) to  
achieve wide power supply operating range, low power con-  
sumption, high noise immunity and symmetric controlled  
rise and fall times. With features such as this the 54C/74C  
logic family is close to ideal for use in digital systems. Func-  
tion and pin out compatibility with series 54/74 devices mini-  
mizes design time for those designers already familiar with  
the standard 54/74 logic family.  
Y
Guaranteed noise margin  
Y
High noise immunity  
0.45 V (typ.)  
CC  
Y
Low power consumption  
10 nW/package (typ.)  
Fan out of 2  
driving 74L  
Y
Low power  
TTL compatibility  
All inputs are protected from damage due to static dis-  
and GND.  
charge by diode clamps to V  
CC  
Connection Diagrams  
Dual-In-Line Packages  
MM54C02/MM74C02  
MM54C00/MM74C00  
MM54C04/MM74C04  
TL/F/5877–1  
TL/F/5877–2  
TL/F/5877–3  
Top View  
Top View  
Top View  
Order Number MM54C00 or  
MM74C00  
Order Number MM54C02 or  
MM74C02  
Order Number MM54C04  
or MM74C04  
MM54C10/MM74C10  
MM54C20/MM74C20  
TL/F/5877–4  
TL/F/5877–5  
Top View  
Top View  
Order Number MM54C10 or  
MM74C10  
Order Number MM54C20 or  
MM74C20  
C
1995 National Semiconductor Corporation  
TL/F/5877  
RRD-B30M115/Printed in U. S. A.  

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