FEDL62Q1500-07
Issue Date: May 19, 2022
ML62Q1500/1800 Group
16-bit micro controller
GENERAL DESCRIPTION
ML62Q1500/1800 Group is a high performance CMOS 16-bit microcontroller equipped with an 16-bit CPU nX-U16/100 and
integrated with program memory(Flash memory), data memory(RAM), data Flash and rich peripheral functions such as the
multiplier/divider, CRC generator, DMA controller, Clock generator, Simplified RTC, Timer, General Purpose Ports, UART,
Synchronous serial port, I2C bus interface unit (Master, Slave), Buzzer, Voltage Level Supervisor(VLS), Successive
approximation type A/D converter, D/A converter , Analog comparator, Safety function(IEC60730/60335 Class B) and so on.
The CPU nX-U16/100 is capable of efficient instruction execution in 1-instruction 1-clock mode by pipeline architecture parallel
processing.
The built-in on-chip debug function enables debugging and programming the software. Also, ISP(In-System Programming)
function supports the Flash programming in production line.
The ML62Q1500/1800 Group has seven packages (48pin - 100pin) and ten kinds of memory sizes(32Kbyte - 512Kbyte).
Table 1 ML62Q1500/1800 Group Product List
48pin
52pin
TQFP52
64pin
QFP64
TQFP64
80pin
100pin
QFP100
TQFP100
Data memory
(RAM)
Program
memory
Data Flash
8Kbyte
TQFP48
QFP80
512Kbyte
384Kbyte
256Kbyte
192Kbyte
160Kbyte
-
-
ML62Q1859
ML62Q1858
ML62Q1557
ML62Q1556
ML62Q1555
-
ML62Q1869
ML62Q1868
ML62Q1567
ML62Q1566
ML62Q1565
ML62Q1564
-
ML62Q1879
ML62Q1878
ML62Q1577
ML62Q1576
ML62Q1575
ML62Q1574
-
32Kbyte
16Kbyte
-
-
-
-
-
-
-
-
16Kbyte
8Kbyte
16Kbyte
8Kbyte
-
-
128Kbyte
96Kbyte
ML62Q1534
-
ML62Q1544
-
ML62Q1554
-
4Kbyte
ML62Q1563
-
ML62Q1573
-
ML62Q1533
ML62Q1532
ML62Q1531
ML62Q1530
ML62Q1543
ML62Q1542
ML62Q1541
ML62Q1540
ML62Q1553
ML62Q1552
ML62Q1551
ML62Q1550
64Kbyte
48Kbyte
32Kbyte
-
-
8Kbyte
-
-
-
-
Please see the page 70 “Notes for product usage” and the page 71 “Notes” in this document on use with this ML62Q1500/1800
group.
FEATURES
• CPU
− 16-bit RISC CPU: nX-U16/100(A35 core)
− Instruction system: 16-bit length instructions
‒ Instruction set: Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations,
bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on
‒ Built-in On-chip debug function
‒ Built-in ISP (In-System Programming) function
‒ Minimum instruction execution time
Approximately 30.5 μs (at 32.768 kHz system clock)
Approximately 62.5ns/41.6ns (at 16 MHz/24MHz system clock)
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