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MK2304S-2LFT PDF预览

MK2304S-2LFT

更新时间: 2024-01-03 00:51:45
品牌 Logo 应用领域
矽成 - ICSI 逻辑集成电路光电二极管驱动
页数 文件大小 规格书
5页 135K
描述
ZERO DELAY, LOW SKEW BUFFER

MK2304S-2LFT 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP, SOP8,.25针数:8
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.23Is Samacsys:N
系列:2304输入调节:STANDARD
JESD-30 代码:R-PDSO-G8JESD-609代码:e0
长度:4.9 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
最大I(ol):0.008 A湿度敏感等级:1
功能数量:1反相输出次数:
端子数量:8实输出次数:4
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP8,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):240电源:3.3 V
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.4 ns
座面最大高度:1.75 mm子类别:Clock Drivers
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:3.9 mm
最小 fmax:133 MHzBase Number Matches:1

MK2304S-2LFT 数据手册

 浏览型号MK2304S-2LFT的Datasheet PDF文件第2页浏览型号MK2304S-2LFT的Datasheet PDF文件第3页浏览型号MK2304S-2LFT的Datasheet PDF文件第4页浏览型号MK2304S-2LFT的Datasheet PDF文件第5页 
MK2304-2  
ZERO DELAY, LOW SKEW BUFFER  
Description  
Features  
The MK2304-2 is a low jitter, low skew, high  
Packaged in 8 pin SOIC  
performance Phase Lock Loop (PLL) based zero delay  
buffer for high speed applications. Based on ICS’  
proprietary low jitter PLL techniques, the device  
provides four low skew outputs at speeds up to 133  
MHz at 3.3 V. The MK2304-2 includes a bank of two  
outputs running at 1/2X. In the zero delay mode, the  
rising edge of the input clock is aligned with the rising  
edges of all 4 outputs. Compared to competitive CMOS  
devices, the MK2304-2 has the lowest jitter.  
Zero input-output delay  
Two 1X outputs plus two 1/2X outputs  
Output to output skew is less than 200 ps  
Output clocks up from 10 MHz to 133 MHz at 3.3 V  
Ability to generate 2X the input  
Full CMOS outputs with 18 mA output drive  
capability at TTL levels at 3.3 V  
TM  
Spread Smart technology works with spread  
The MK2304-2 PLL enters a power-down state when  
there are no rising edges on the REF input. In this  
mode, all outputs are tri-stated and the PLL is turned  
off, resulting in leass than 25 µA of current draw.  
spectrum clock generators  
Advanced, low power, sub micron CMOS process  
Operating voltage of 3.3 V  
Available in industial temperature operation  
Available in Pb (lead) free package  
Low Standby Current  
ICS manufactures the largest variety of clock  
generators and buffers and is the largest clock supplier  
in the world.  
Block Diagram  
VDD  
1
FBIN  
PLL  
CLKIN  
CLKA1  
CLKA2  
BANK  
A
CLKB1  
CLKB2  
BANK  
B
/2  
1
GND  
MDS 2304-2 C  
1
Revision 050306  
Integrated Circuit Systems 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com  

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