Datasheet > MK2308S-1T

MK2308S-1T

更新时间： 2024-09-25 22:32:43

品牌	Logo	应用领域
矽成 - ICSI		逻辑集成电路光电二极管驱动
页数	文件大小	规格书
6页	139K
描述
3.3 VOLT ZERO DELAY, LOW SKEW BUFFER

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MK2308S-1T 数据手册

MK2308-1

3.3 VOLT ZERO DELAY, LOW SKEW BUFFER

Description

Features

The MK2308-1 is a low phase noise, high-speed PLL

based, 8-output, low-skew zero delay buffer. Based on

ICS’ proprietary low jitter Phase Locked Loop (PLL)

techniques, the device provides eight low skew outputs

at speeds up to 133 MHz at 3.3 V. The outputs can be

generated from the PLL (for zero delay), or directly

from the input (for testing), and can be set to tri-state

mode or to stop at a low level. For normal operation as

a zero delay buffer, any output clock is tied to the FBIN

pin.

• Clock outputs from 10 to 133 MHz

• Zero input-output delay

• Eight low skew (<200 ps) outputs

• Device-to-device skew <700 ps

• Full CMOS outputs with 25 mA output drive

capability at TTL levels

• 5 V tolerant FBIN and CLKIN pins

• Tri-state mode for board-level testing

• Advanced, low power, sub-micron CMOS process

• Operating voltage of 3.3 V

ICS manufactures a variety of clock generators and

buffers.

• Industrial temperature range available

• Packaged in 16-pin SOIC

Block Diagram

VDD

Control

Logic

S2, S1

CLKA1

CLKA2

CLKA3

CLKIN

FBIN

CLKA4

Clock

Synthesis

PLL

CLKB1

CLKB2

CLKB3

CLKB4

Feedback is shown from CLKB4 for

illustration, but may come from any output.

GND

MDS 2308-1 A

Revision 100603

Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 295-9800 ● www.icst.com

12 3 4 5 6

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