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MK2308S-2I PDF预览

MK2308S-2I

更新时间: 2024-09-26 11:52:27
品牌 Logo 应用领域
矽成 - ICSI /
页数 文件大小 规格书
5页 122K
描述
ZERO DELAY LOW SKEW BUFFER

MK2308S-2I 数据手册

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MK2308-2  
ZERO DELAY, LOW SKEW BUFFER  
Description  
Features  
The MK2308-2 is a low jitter, low skew, high  
Packaged in 16-pin SOIC  
performance Phase-Lock Loop (PLL) based zero delay  
buffer for high speed applications. Based on ICS’  
proprietary low jitter PLL techniques, the device  
provides eight low skew outputs at speeds up to 160  
MHz at 3.3 V. The MK2308-2 includes a bank of four  
outputs running at 1/2X. In the zero delay mode, the  
rising edge of the input clock is aligned with the rising  
edges of all eight outputs. Compared to competitive  
CMOS devices, the MK2308-2 has the lowest jitter.  
Zero input-output delay  
Four 1X outputs plus four 1/2X outputs  
Output to output skew is less than 250 ps  
Output clocks up to 160 MHz at 3.3 V  
Ability to generate 2X the input  
Full CMOS outputs with 18 mA output drive  
capability at TTL levels at 3.3 V  
TM  
Spread Smart technology works with spread  
spectrum clock generators  
Advanced, low power, sub micron CMOS process  
Operating voltage of 3.3 V or 5 V  
Block Diagram  
VDD  
2
CLKA1  
CLKA2  
CLKA3  
CLKA4  
FBIN  
PLL  
BANK  
A
CLKIN  
/2  
CLKB1  
CLKB2  
CLKB3  
CLKB4  
BANK  
B
Control  
Logic  
2
S2, S1  
2
GND  
MDS 2308-2 B  
1
Revision 111103  
Integrated Circuit Systems 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com  

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