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MH64S64APFH-6 PDF预览

MH64S64APFH-6

更新时间: 2024-11-18 22:26:39
品牌 Logo 应用领域
三菱 - MITSUBISHI 动态存储器
页数 文件大小 规格书
52页 599K
描述
4294967296-BIT (67108864 - WORD BY 64-BIT)SynchronousDRAM

MH64S64APFH-6 技术参数

生命周期:Obsolete零件包装代码:DIMM
包装说明:DIMM, DIMM144,32针数:144
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.36风险等级:5.84
访问模式:DUAL BANK PAGE BURST最长访问时间:5.4 ns
其他特性:AUTO/SELF REFRESH最大时钟频率 (fCLK):133 MHz
I/O 类型:COMMONJESD-30 代码:R-XDMA-N144
内存密度:4294967296 bit内存集成电路类型:SYNCHRONOUS DRAM MODULE
内存宽度:64功能数量:1
端口数量:1端子数量:144
字数:67108864 words字数代码:64000000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:64MX64
输出特性:3-STATE封装主体材料:UNSPECIFIED
封装代码:DIMM封装等效代码:DIMM144,32
封装形状:RECTANGULAR封装形式:MICROELECTRONIC ASSEMBLY
电源:3.3 V认证状态:Not Qualified
刷新周期:8192自我刷新:YES
最大待机电流:0.016 A子类别:DRAMs
最大压摆率:2.88 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:NO技术:CMOS
温度等级:COMMERCIAL端子形式:NO LEAD
端子节距:0.8 mm端子位置:DUAL
Base Number Matches:1

MH64S64APFH-6 数据手册

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Preliminary Spec.  
MITSUBISHI LSIs  
Some contents are subject to change without notice.  
MH64S64APFH-6,-6L,-7,-7L  
4294967296-BIT (67108864 - WORD BY 64-BIT)SynchronousDRAM  
DESCRIPTION  
Utilizes industry standard 32M x 8 Sy nchronous DRAMs  
Small TSOP and industry standard EEPROM in TSSOP  
The MH64S64APFH is 67108864 - word by 64-bit  
Synchronous DRAM module. This consists of  
sixteen industry standard 32Mx8 Synchronous  
DRAMs in Small TSOP and one industory  
standard EEPROM in TSSOP.  
144-pin (72-pin dual in-line package)  
single 3.3V±0.3V power supply  
Max. Clock frequency -6:133MHz,-7:100MHz  
The mounting of Small TSOP on a card edge  
Dual Inline package provides any application  
where high densities and large quantities of  
memory are required.  
Fully synchronous operation referenced to clock rising  
edge  
This is a socket type - memory modules, suitable  
for easy interchange or addition of modules.  
4 bank operation controlled by BA0,1(Bank Address)  
/CAS latency- 2/3(programmable)  
Burst length- 1/2/4/8/Full Page(programmable)  
Burst type- sequential / interleave(programmable)  
Column access - random  
FEATURES  
CLK Access Time  
Frequency  
(Component SDRAM)  
5.4ns(CL=3)  
6.0ns(CL=2)  
-6,-6L  
-7,-7L  
133MHz  
100MHz  
Auto precharge / All bank precharge controlled by A10  
Auto refresh and Self refresh  
8192 refresh cycle /64ms  
LVTTL Interface  
APPLICATION  
main memory or graphic memory in computer systems  
PCB Outline  
(Front)  
(Back)  
1
2
143  
144  
16.Apr.2000  
MITSUBISHI  
ELECTRIC  
MIT-DS-0392-0.1  
(
/ 52 )  
1

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