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MH64S72PHH-6 PDF预览

MH64S72PHH-6

更新时间: 2024-11-19 21:11:35
品牌 Logo 应用领域
三菱 - MITSUBISHI 时钟动态存储器内存集成电路
页数 文件大小 规格书
51页 621K
描述
Synchronous DRAM Module, 64708864X72, 5.4ns, CMOS, DIMM-168

MH64S72PHH-6 技术参数

生命周期:Obsolete零件包装代码:DIMM
包装说明:DIMM, DIMM168针数:168
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.36风险等级:5.84
访问模式:DUAL BANK PAGE BURST最长访问时间:5.4 ns
其他特性:AUTO/SELF REFRESH最大时钟频率 (fCLK):133 MHz
I/O 类型:COMMONJESD-30 代码:R-XDMA-N168
内存密度:4659038208 bit内存集成电路类型:SYNCHRONOUS DRAM MODULE
内存宽度:72功能数量:1
端口数量:2端子数量:168
字数:64708864 words字数代码:64708864
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:64708864X72
输出特性:3-STATE封装主体材料:UNSPECIFIED
封装代码:DIMM封装等效代码:DIMM168
封装形状:RECTANGULAR封装形式:MICROELECTRONIC ASSEMBLY
电源:3.3 V认证状态:Not Qualified
刷新周期:8192自我刷新:YES
最大待机电流:0.018 A子类别:DRAMs
最大压摆率:3.24 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:NO技术:CMOS
温度等级:COMMERCIAL端子形式:NO LEAD
端子节距:1.27 mm端子位置:DUAL
Base Number Matches:1

MH64S72PHH-6 数据手册

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Preliminary Spec.  
MITSUBISHI LSIs  
Some contents are subject to change without notice.  
MH64S72PHH -5,-5L,-6,-6L,-7,-7L  
4,659,038,208-BIT (64,708,864 - WORD BY 72-BIT)Synchronous DRAM  
DESCRIPTION  
The MH64S72PHH is 64708864 - word by 72-bit  
Synchronous DRAM module. This consists of  
eighteen industry standard 32Mx8 Synchronous  
DRAMs in TSOP and one industory standard  
EEPROM in TSSOP.  
The mounting of TSOP on a card edge Dual  
Inline package provides any application where  
high densities and large quantities of memory are  
required.  
85pin  
1pin  
This is a socket type - memory modules, suitable  
for easy interchange or addition of modules.  
94pin  
95pin  
10pin  
11pin  
FEATURES  
CLK Access Time  
Frequency  
(Component SDRAM)  
-5,-5L  
-6,-6L  
-7,-7L  
5.4ns(CL=2)  
5.4ns(CL=3)  
6.0ns(CL=2)  
133MHz  
133MHz  
100MHz  
124pin  
125pin  
40pin  
41pin  
Utilizes industry standard 32M x 8 Sy nchronous DRAMs  
TSOP and industry standard EEPROM in TSSOP  
168-pin (84-pin dual in-line package)  
single 3.3V±0.3V power supply  
Max. Clock frequency -5,5L,-6,6L:133MHz,  
-7,7L:100MHz  
Fully synchronous operation referenced to clock  
rising edge  
4 bank operation controlled by BA0,1(Bank Address)  
/CAS latency- 2/3(programmable)  
Burst length- 1/2/4/8/Full Page(programmable)  
Burst type- sequential / interleave(programmable)  
Column access - random  
84pin  
168pin  
Auto precharge / All bank precharge controlled  
by A10  
Auto refresh and Self refresh  
8192 refresh cycle /64ms  
LVTTL Interface  
Discrete IC and module design conform to  
PC100/PC133 specification.  
APPLICATION  
PC main memory  
MITSUBISHI  
MIT-DS-0426-0.1  
13.Jul.2001  
ELECTRIC  
( 1 / 51 )  

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