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MH28S72PJG-6 PDF预览

MH28S72PJG-6

更新时间: 2024-10-27 22:26:31
品牌 Logo 应用领域
三菱 - MITSUBISHI /
页数 文件大小 规格书
57页 951K
描述
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

MH28S72PJG-6 技术参数

生命周期:Obsolete零件包装代码:DIMM
包装说明:DIMM, DIMM168针数:168
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.36风险等级:5.84
访问模式:DUAL BANK PAGE BURST最长访问时间:5.4 ns
其他特性:AUTO/SELF REFRESH最大时钟频率 (fCLK):133 MHz
I/O 类型:COMMONJESD-30 代码:R-XDMA-N168
内存密度:9663676416 bit内存集成电路类型:SYNCHRONOUS DRAM MODULE
内存宽度:72功能数量:1
端口数量:1端子数量:168
字数:134217728 words字数代码:128000000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:128MX72
输出特性:3-STATE封装主体材料:UNSPECIFIED
封装代码:DIMM封装等效代码:DIMM168
封装形状:RECTANGULAR封装形式:MICROELECTRONIC ASSEMBLY
电源:3.3 V认证状态:Not Qualified
刷新周期:8192自我刷新:YES
最大待机电流:0.351 A子类别:DRAMs
最大压摆率:6.795 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:NO技术:CMOS
温度等级:COMMERCIAL端子形式:NO LEAD
端子节距:1.27 mm端子位置:DUAL
Base Number Matches:1

MH28S72PJG-6 数据手册

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Preliminary Spec.  
MITSUBISHI LSIs  
Some contents are subject to change without notice.  
MH28S72PJG -5,-6,-7  
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM  
DESCRIPTION  
The MH28S72PJG is 134,217,728 - word x 72-bit  
Synchronous DRAM stacked structural module. This  
consist of thirty-six industry standard 64M x 4  
Synchronous DRAMs in TSOP.  
The stacked structure of TSOP on a card edge dual in-  
line package prov ides any application where high  
densities and large of quantities memory are required.  
This is a socket-type memory module ,suitable for  
easy interchange or addition of module.  
85pin  
1pin  
FEATURES  
94pin  
95pin  
10pin  
11pin  
CLK Access Time  
Frequency  
(at Latch mode,Components)  
133MHz  
133MHz  
100MHz  
5.4ns(CL=3)  
5.4ns(CL=4)  
-5  
-6  
-7  
6.0ns(CL=3)  
124pin  
125pin  
40pin  
41pin  
Utilizes industry standard 64M X 4 Synchronous DRAMs in  
TSOP package , industry standard Resister in TSSOP package ,  
and industry standard PLL in TSSOP package.  
Single 3.3V +/- 0.3V supply  
Burst length 1/2/4/8/Full Page (programmable)  
Burst type sequential / interleave (programmable)  
Column access random  
Burst W rite / Single W rite (programmable)  
Auto precharge / Auto bank precharge controlled by A10  
Auto refresh and Self refresh  
LVTTL Interface  
8192 refresh cycles every 64ms  
APPLICATION  
84pin  
168pin  
Main memory unit for computers, Microcomputer memory.  
1
27/Mar. /2001  
MIT-DS-406-0.2  
MITSUBISHI  
ELECTRIC  

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