MH28S72PJG-7

更新时间： 2024-10-27 22:26:31

品牌	Logo	应用领域
三菱 - MITSUBISHI		/
页数	文件大小	规格书
57页	951K
描述
9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

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MH28S72PJG-7 数据手册

Preliminary Spec.

MITSUBISHI LSIs

Some contents are subject to change without notice.

MH28S72PJG -5,-6,-7

9,663,676,416-BIT ( 134,217,728-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

DESCRIPTION

The MH28S72PJG is 134,217,728 - word x 72-bit

Synchronous DRAM stacked structural module. This

consist of thirty-six industry standard 64M x 4

Synchronous DRAMs in TSOP.

The stacked structure of TSOP on a card edge dual in-

line package prov ides any application where high

densities and large of quantities memory are required.

This is a socket-type memory module ,suitable for

easy interchange or addition of module.

85pin

1pin

FEATURES

94pin

95pin

10pin

11pin

CLK Access Time

Frequency

(at Latch mode,Components)

133MHz

100MHz

5.4ns(CL=3)

5.4ns(CL=4)

-5

-6

-7

6.0ns(CL=3)

124pin

125pin

40pin

41pin

Utilizes industry standard 64M X 4 Synchronous DRAMs in

TSOP package , industry standard Resister in TSSOP package ,

and industry standard PLL in TSSOP package.

Single 3.3V +/- 0.3V supply

Burst length 1/2/4/8/Full Page (programmable)

Burst type sequential / interleave (programmable)

Column access random

Burst W rite / Single W rite (programmable)

Auto precharge / Auto bank precharge controlled by A10

Auto refresh and Self refresh

LVTTL Interface

8192 refresh cycles every 64ms

APPLICATION

84pin

168pin

Main memory unit for computers, Microcomputer memory.

27/Mar. /2001

MIT-DS-406-0.2

MITSUBISHI

ELECTRIC

12 3 4 5 6 7...57

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MH28TAD-R1.0000MHZ	MTRONPTI	获取价格	Oscillator,
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MH28TAD-RFREQ1	MTRONPTI	获取价格	CMOS/TTL Output Clock Oscillator, 1MHz Min, 50MHz Max, HALF SIZE, NICKEL HEADER, DIP-4
MH28TAD-RFREQ2	MTRONPTI	获取价格	CMOS/TTL Output Clock Oscillator, 50.001MHz Min, 60MHz Max, HALF SIZE, NICKEL HEADER, DIP-