Datasheet > MEC1310-NU-TR

MEC1310-NU-TR

更新时间： 2024-11-03 21:09:35

品牌	Logo	应用领域
美国微芯 - MICROCHIP		外围集成电路
页数	文件大小	规格书
10页	194K
描述
IC EMBEDDED CTLR 128TQFP

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技术参数
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MEC1310-NU-TR 技术参数

是否无铅：	不含铅	生命周期：	Active
包装说明：	TFQFP,	Reach Compliance Code：	compliant
Factory Lead Time：	6 weeks	风险等级：	5.06
JESD-30 代码：	S-PQFP-G128	长度：	14 mm
端子数量：	128	最高工作温度：	85 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	TFQFP	封装形状：	SQUARE
封装形式：	FLATPACK, THIN PROFILE, FINE PITCH	筛选级别：	TS 16949
座面最大高度：	1.2 mm	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	OTHER	端子形式：	GULL WING
端子节距：	0.4 mm	端子位置：	QUAD
宽度：	14 mm	uPs/uCs/外围集成电路类型：	MICROPROCESSOR CIRCUIT
Base Number Matches：	1

MEC1310-NU-TR 数据手册

MEC1310

Keyboard and Embedded Controller for Notebook PC

- Two 16-Bit Timer/Counters

Product Features

- Integrated Full-Duplex Serial Port Interface

- Seventy-Three 8051 Interrupt Sources

• 3.3V Operation with 5V Tolerant Buffers on PS/2

pins

- Thirty-Two 8-Bit, Host/8051 Mailbox Regis-

ters

• ACPI 1.0/2.0 PC99/PC2001 Compliant

• LPC Interface with Clock Run Support

- Sixty-Four Maskable Hardware Wake-Up

Events

- Supports LPC Bus frequencies of 19.2MHz to

33MHz

- Fast GATEA20

- Serial IRQ Interface Compatible with Serial-

ized IRQ Support for PCI Systems

- Fast CPU_RESET

- Multiple Clock Sources and Operating Fre-

quencies

- 15 Direct IRQs

- ACPI SCI Interface

- IDLE and SLEEP Modes

- Trace FIFO Debug Port

- nSMI output and supporting PM registers

- Shadowed write only registers

• Internal 64K SRAM in MEC1310

• Accurate Fail-Safe Ring Oscillator

- Single Clock source for most 8051 and SIO

functions

- Loaded at VCC1 power from the HOST/8051

SPI Memory Interface

- Provides 2% frequency accuracy

- Lock Bit provides status

- Provides 64KB of 8051 program space

- 32k-Byte region shared with 8051data space

• HOST/8051 SPI Memory Interface

- 32.768KHz-input clock

–

Single ended input

Compatible with south bridge SUSCLK/

RSMRST# gating rules

- 3-pin Full Duplex serial communication inter-

face.

–

replacement 32K distribution available when

RSMRST# is asserted

Very low power state with only external 32K clock

distributed

- One Chip Select Pins

- Fully 8051 Controlled

- Hardware Support for two SPI Flash Configu-

rations:

• Integrated Standby Power Reset Generator

- VCC1_RST# open drain output

- Accepts External driven Reset

• VCC0 Backed Resources

–

Switched SPI Flash Configuration

Parallel Shared SPI Flash Configuration

Debug Programming Interface

• Two Power Planes

- 64 Byte VCC0 Backed Registers

- VCC0 Backed Status Register

• Three 8584-Style I²C/SMBus Controllers

- 8051 Controlled Logic Allows I²C/SMBus

Master or Slave Operation

- I²C/SMBus Controllers are Fully Operational

on Standby Power

- Low Standby Current in Sleep Mode

• Three ACPI Embedded Controller Interface

• Configuration Register Set Compatible with ISA

Plug-and-Play Standard (Version 1.0a)

• High-Performance Embedded 8051 Keyboard

and System Controller

- Provides System Power Management

- System Watch Dog Timer (WDT)

- 8042 Style Host Interface

- Two Controllers with 2 Sets of Dedicated Pins

per I²C/SMBus Controller

- One Controller with one Set of Dedicated

Pins per I²C/SMBus Controller

- Supports Interrupt and Polling Access

- 1024 Boot /ROM

• Four independent Hardware Driven PS/2 Ports

- 256 Bytes Data RAM

- GPIO signal function associated with each

- On-Chip Memory-Mapped Control Registers

- Access to VCC0 Backed Registers

- Up to 18x8 Keyboard Scan Matrix

• PECI Interface 2.0

 2014 Microchip Technology Inc.

DS00001768A-page 1

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中文翻译

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