Datasheet > MCM64ZA18TQ8.5R

MCM64ZA18TQ8.5R

更新时间： 2024-11-25 15:41:11

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		静态存储器内存集成电路
页数	文件大小	规格书
34页	230K
描述
1MX18 ZBT SRAM, 8.5ns, PQFP100, TQFP-100

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技术参数
数据手册

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MCM64ZA18TQ8.5R 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	LQFP, QFP100,.63X.87
针数：	100	Reach Compliance Code：	unknown
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
风险等级：	5.92	最长访问时间：	8.5 ns
其他特性：	ALSO REQUIRES 2.5V I/O SUPPLY	I/O 类型：	COMMON
JESD-30 代码：	R-PQFP-G100	JESD-609代码：	e0
长度：	20 mm	内存密度：	18874368 bit
内存集成电路类型：	ZBT SRAM	内存宽度：	18
功能数量：	1	端子数量：	100
字数：	1048576 words	字数代码：	1000000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	1MX18
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	LQFP	封装等效代码：	QFP100,.63X.87
封装形状：	RECTANGULAR	封装形式：	FLATPACK, LOW PROFILE
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	2.5 V	认证状态：	Not Qualified
座面最大高度：	1.6 mm	最大待机电流：	0.01 A
最小待机电流：	2.4 V	子类别：	SRAMs
最大压摆率：	0.28 mA	最大供电电压 (Vsup)：	2.625 V
最小供电电压 (Vsup)：	2.375 V	标称供电电压 (Vsup)：	2.5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	14 mm	Base Number Matches：	1

MCM64ZA18TQ8.5R 数据手册

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Order this document

by MCM64Z936/D

MCM64Z936

MCM64ZA18

Product Preview

512K x 36 and 1M x 18 Bit

ZBTr Fast Static RAM

The ZBT RAM is a 16M–bit synchronous fast static RAM designed to provide

Zero Bus Turnaroundr. The ZBT RAM allows 100% use of bus cycles during

back–to–back read/write and write/read cycles. The MCM64Z936 (organized as

512K words by 36 bits) and the MCM64ZA18 (organized as 1M words by 18 bits)

are fabricated in Motorola’s high performance silicon gate CMOS technology.

Thisdeviceintegratesinputregisters, anoutputregister, a2–bitaddresscounter,

and high speed SRAM onto a single monolithic circuit for reduced parts count in

communication applications. Synchronous design allows precise cycle control

with the use of an external positive–edge–triggered clock (CK). CMOS circuitry

reduces the overall power consumption of the integrated functions for greater

reliability.

TQ PACKAGE

TQFP

CASE 983A–01

ZP PACKAGE

PBGA

CASE 999–02

Addresses (SA), data inputs (DQ), and all control signals except output enable

(G), sleep mode (ZZ), and linear burst order (LBO) are clock (CK) controlled

through positive–edge–triggered noninverting registers.

Write cycles are internally self–timed and are initiated by the rising edge of the

clock (CK) input. This feature eliminates complex off–chip write pulse generation

and provides increased timing flexibility for incoming signals. Write data is

supplied to the memory one cycle after the write sequence initiation for the flow–

through mode, and two cycles after the write sequence initiation for the pipelined

mode.

For flow–through read cycles, the SRAM allows output data to simply flow freely from the memory

array. For pipelined read cycles, the SRAM output data is temporarily stored by an edge–triggered

output register and then released to the output buffers at the next rising edge of clock (CK).

TheMCM64Z936andMCM64ZA18operatefroma2.5Vcorepowersupply, andalloutputsoper-

ate on a 2.5 V power supply. All inputs and outputs are JEDEC Standard JESD8–5 compatible.

•

2.5 V ±5% Core Power Supply, 2.5 V I/O Supply

MCM64Z936/A18–7 = 7 ns Flow–Through Access/2.6 ns Pipelined Access (225 MHz)

MCM64Z936/A18–8 = 8 ns Flow–Through Access/3 ns Pipelined Access (200 MHz)

MCM64Z936/A18–8.5 = 8.5 ns Flow–Through Access/3.5 ns Pipelined Access (166 MHz)

Selectable Read/Write Functionality (Flow–Through/Pipelined)

Selectable Burst Sequencing Order (Linear/Interleaved)

Internally Self–Timed Write Cycle

Two–Cycle Deselect (Pipelined)

Byte Write Control

ADV Controlled Burst

Simplified JTAG

•

100–Pin TQFP and 119–Bump PBGA Packages

ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc., and the architecture is supported by

Micron Technology, Inc. and Motorola, Inc.

This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.

1/14/00

Motorola, Inc. 2000

MOTOROLA FAST SRAM

MCM64Z936•MCM64ZA18

12 3 4 5 6 7...34

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与MCM64ZA18TQ8.5R相关器件

型号	品牌	获取价格	描述	数据表
MCM64ZA18ZP8.5R	MOTOROLA	获取价格	1MX18 ZBT SRAM, 8.5ns, PBGA119, PLASTIC, BGA-119
MCM64ZA18ZP8R	MOTOROLA	获取价格	1MX18 ZBT SRAM, 8ns, PBGA119, PLASTIC, BGA-119
MCM66710C	MOTOROLA	获取价格	Memory IC, MOS, CDIP24
MCM66710L	MOTOROLA	获取价格	Memory IC, MOS, CDIP24
MCM66710P	MOTOROLA	获取价格	Memory IC, MOS, PDIP24
MCM66714L	MOTOROLA	获取价格	Memory IC, MOS, CDIP24
MCM66714P	MOTOROLA	获取价格	Memory IC, MOS, PDIP24
MCM66720C	MOTOROLA	获取价格	Memory IC, MOS, CDIP24
MCM66720P	MOTOROLA	获取价格	Memory IC, MOS, PDIP24
MCM66730P	MOTOROLA	获取价格	Memory IC, MOS, PDIP24

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