Datasheet > MCM64Z836TQ7R

MCM64Z836TQ7R

更新时间： 2024-11-18 20:18:59

品牌	Logo	应用领域
恩智浦 - NXP		静态存储器内存集成电路
页数	文件大小	规格书
34页	740K
描述
256KX36 ZBT SRAM, 7ns, PQFP100, PLASTIC, TQFP-100

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

MCM64Z836TQ7R 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Transferred	零件包装代码：	QFP
包装说明：	PLASTIC, TQFP-100	针数：	100
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.53
Is Samacsys：	N	最长访问时间：	7 ns
I/O 类型：	COMMON	JESD-30 代码：	R-PQFP-G100
长度：	20 mm	内存密度：	9437184 bit
内存集成电路类型：	ZBT SRAM	内存宽度：	36
湿度敏感等级：	1	功能数量：	1
端子数量：	100	字数：	262144 words
字数代码：	256000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	256KX36	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装等效代码：	QFP100,.63X.87	封装形状：	RECTANGULAR
封装形式：	FLATPACK, LOW PROFILE	并行/串行：	SERIAL
峰值回流温度（摄氏度）：	225	电源：	2.5 V
认证状态：	Not Qualified	座面最大高度：	1.6 mm
最大待机电流：	0.01 A	最小待机电流：	2.3 V
子类别：	SRAMs	最大压摆率：	0.27 mA
最大供电电压 (Vsup)：	2.7 V	最小供电电压 (Vsup)：	2.3 V
标称供电电压 (Vsup)：	2.5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	14 mm	Base Number Matches：	1

MCM64Z836TQ7R 数据手册

Freescale Semiconductor, Inc.

SEMICONDUCTOR TECHNICAL DATA

Order this document

by MCM64Z836/D

MCM64Z836

MCM64Z918

Product Preview

256K x 36 and 512K x 18 Bit

ZBT Fast Static RAM

The ZBT RAM is an 8M–bit synchronous fast static RAM designed to provide

Zero Bus Turnaround . The ZBT RAM allows 100% use of bus cycles during

back–to–back read/write and write/read cycles. The MCM64Z836 (organized as

256K words by 36 bits) and the MCM64Z918 (organized as 512K words by 18

bits) are fabricated in Motorola’s high performance silicon gate CMOS tech-

nology. This device integrates input registers, an output register, a 2–bit address

counter, and high speed SRAM onto a single monolithic circuit for reduced parts

count in communication applications. Synchronous design allows precise cycle

control with the use of an external positive–edge–triggered clock (CK). CMOS

circuitry reduces the overall power consumption of the integrated functions for

greater reliability.

TQ PACKAGE

TQFP

CASE 983A–01

ZP PACKAGE

PBGA

CASE 999–02

Addresses (SA), data inputs (DQ), and all control signals except output enable

(G) and linear burst order (LBO) are clock (CK) controlled through positive–

edge–triggered noninverting registers.

Write cycles are internally self–timed and are initiated by the rising edge of the

clock (CK) input. This feature eliminates complex off–chip write pulse generation

and provides increased timing flexibility for incoming signals. Write data is

supplied to the memory one cycle after the write sequence initiation for the flow–

throughdevice, andtwocyclesafterthewritesequenceinitiationforthepipelined

device.

For flow–through read cycles, the SRAM allows output data to simply flow freely from the memory

array. For pipelined read cycles, the SRAM output data is temporarily stored by an edge–triggered

output register and then released to the output buffers at the next rising edge of clock (CK).

The MCM64Z836 and MCM64Z918 operate from a 2.5 V core power supply and all outputs oper-

ate on a 2.5 V power supply. All inputs and outputs are JEDEC Standard JESD8–5 compatible.

•

2.5 V ±200 mV Core Power Supply, 2.5 V I/O Supply

MCM64Z836/918–7 = 7 ns Flow–Through Access/2.6 ns Pipelined Access (225 MHz)

MCM64Z836/918–8 = 8 ns Flow–Through Access/3 ns Pipelined Access (200 MHz)

MCM64Z836/918–8.5 = 8.5 ns Flow–Through Access/3.5 ns Pipelined Access (166 MHz)

Selectable Read/Write Functionality (Flow–Through/Pipelined)

Selectable Burst Sequencing Order (Linear/Interleaved)

Internally Self–Timed Write Cycle

Two–Cycle Deselect (Pipelined)

Byte Write Control

ADV Controlled Burst

Simplified JTAG

•

100–Pin TQFP and 119–Bump PBGA Packages

ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc., and the architecture is supported by

Micron Technology, Inc. and Motorola, Inc.

This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.

REV 3

9/1/99

Motorola, Inc. 1999

MOTOROLA FAST SRAM

MCM64Z836•MCM64Z918

For More Information On This Product,

Go to: www.freescale.com

12 3 4 5 6 7...34

中文翻译

下载PDF

与MCM64Z836TQ7R相关器件

型号	品牌	获取价格	描述	数据表
MCM64Z836TQ8	FREESCALE	获取价格	256K x 36 and 512K x 18 Bit ZBT Fast Static RAM
MCM64Z836TQ8.5	FREESCALE	获取价格	256K x 36 and 512K x 18 Bit ZBT Fast Static RAM
MCM64Z836TQ8.5R	FREESCALE	获取价格	256K x 36 and 512K x 18 Bit ZBT Fast Static RAM
MCM64Z836TQ8.5R	NXP	获取价格	256KX36 ZBT SRAM, 8.5ns, PQFP100, PLASTIC, TQFP-100
MCM64Z836TQ8R	NXP	获取价格	256KX36 ZBT SRAM, 8ns, PQFP100, PLASTIC, TQFP-100
MCM64Z836TQ8R	FREESCALE	获取价格	256K x 36 and 512K x 18 Bit ZBT Fast Static RAM
MCM64Z836ZP166	MOTOROLA	获取价格	ZBT SRAM, 256KX36, 3.6ns, CMOS, PBGA119, PLASTIC, BGA-119
MCM64Z836ZP166R	MOTOROLA	获取价格	ZBT SRAM, 256KX36, 3.6ns, CMOS, PBGA119, PLASTIC, BGA-119
MCM64Z836ZP7	NXP	获取价格	256KX36 ZBT SRAM, 7ns, PBGA119, BUMP, PLASTIC, BGA-119
MCM64Z836ZP7	FREESCALE	获取价格	256K x 36 and 512K x 18 Bit ZBT Fast Static RAM

与MCM64Z836TQ7R相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

17
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

12
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

42
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

37

产品中心

服务支持

精选活动

关于我们

帮助中心

MCM64Z836TQ7R

MCM64Z836TQ7R 技术参数

MCM64Z836TQ7R 数据手册

与MCM64Z836TQ7R相关器件

与MCM64Z836TQ7R相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

MCM64Z836TQ7R

MCM64Z836TQ7R 技术参数

MCM64Z836TQ7R 数据手册

与MCM64Z836TQ7R相关器件

与MCM64Z836TQ7R相关文章

您还可以找

您在本页遇到什么问题？