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MCM64E836FC3.3R PDF预览

MCM64E836FC3.3R

更新时间: 2024-11-24 19:07:59
品牌 Logo 应用领域
恩智浦 - NXP 时钟双倍数据速率静态存储器内存集成电路
页数 文件大小 规格书
22页 424K
描述
256KX36 DDR SRAM, PBGA153, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, FLIP CHIP, BGA-153

MCM64E836FC3.3R 技术参数

生命周期:Transferred零件包装代码:BGA
包装说明:BGA,针数:153
Reach Compliance Code:unknown风险等级:5.66
Is Samacsys:N其他特性:PIPELINED ARCHITECTURE
JESD-30 代码:R-PBGA-B153长度:22 mm
内存密度:9437184 bit内存集成电路类型:DDR SRAM
内存宽度:36功能数量:1
端子数量:153字数:262144 words
字数代码:256000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:256KX36封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装形状:RECTANGULAR
封装形式:GRID ARRAY并行/串行:PARALLEL
认证状态:Not Qualified座面最大高度:2.77 mm
最大供电电压 (Vsup):2.625 V最小供电电压 (Vsup):2.375 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:BALL端子节距:1.27 mm
端子位置:BOTTOM宽度:14 mm
Base Number Matches:1

MCM64E836FC3.3R 数据手册

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Freescale Semiconductor, Inc.  
SEMICONDUCTOR TECHNICAL DATA  
MOTOROLA  
Order this document  
by MCM64E918/D  
MCM64E918  
MCM64E836  
8MB Double Data Rate HSTL I/O  
Fast SRAM  
The MCM64E918/MCM64E836 are 8M–bit pipelined burst synchronous late  
write fast static RAMs designed to provide very high data bandwidth in secondary  
cache applications. The MCM64E918 (organized as 512K words by 18 bits wide)  
and the MCM64E836 (organized as 256K words by 36 bits wide) are fabricated  
in Motorola’s high performance silicon gate MOS technology.  
The differential clock (CK) inputs control the timing of read/write operations of  
the RAM. At the rising edge of CK, all addresses and burst control inputs are reg-  
istered. An internal buffer and special logic enables the memory to accept write  
data on the rising or rising and falling edges of the clock, a cycle following address  
and control signals. Read data is driven on the rising or rising and falling edges  
of the CK clock and is referenced to echo clock (CQ and CQ) outputs.  
The MCM64E918/MCM64E836 have HSTL inputs and outputs. The adjust-  
able input trip–point (Vref) and output power supply voltage (VDDQ) gives  
the system designer greater flexibility in optimizing system performance.  
The impedance of the output buffers is programmable, allowing the outputs to  
match the impedance of the circuit traces, which reduces signal reflections.  
FC PACKAGE  
FLIPPED CHIP PBGA  
CASE 1107C–03  
Single 2.5 V 5% Power Supply  
Single Data Rate (SDR) and Double Data Rate (DDR) Burst Read and  
Write  
Pin Selectable Linear or Interleaved Burst Order  
Four Tick Burst with Automatic Wrap–Around  
Differential Clock Inputs  
Active High and Active Low Echo Clock Outputs  
1.8 V Expanded HSTL — I/O (JEDEC Standard JESD8–6 Class I  
Compatible)  
1.8 V Expanded HSTL — Compatible Programmable Impedance Output  
Drivers  
Pipelined (Register to Register) Synchronous Operation  
Boundary Scan (JTAG) IEEE 1149.1 Compatible  
Stop Clock Functionality Supported  
Optional x18 or x36 Organization  
MCM64E918/MCM64E836–3.0 = 3.0 ns Clock Cycle Time  
MCM64E918/MCM64E836–3.3 = 3.3 ns Clock Cycle Time  
MCM64E918/MCM64E836–4.0 = 4.0 ns Clock Cycle Time  
9 x 17 (153) Bump, 50 mil (1.27 mm) Pitch, 14 mm x 22 mm Flipped Chip  
Plastic Ball Grid Array (PBGA) package  
REV2  
7/2/01  
Motorola, Inc. 2001  
For More Information On This Product,  
Go to: www.freescale.com  

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