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MCM63Z818TQ100 PDF预览

MCM63Z818TQ100

更新时间: 2024-11-24 22:15:03
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 存储内存集成电路静态存储器
页数 文件大小 规格书
20页 223K
描述
128K x 36 and 256K x 18 Bit Pipelined ZBT RAM Synchronous Fast Static RAM

MCM63Z818TQ100 技术参数

是否Rohs认证:不符合生命周期:Obsolete
包装说明:TQFP-100Reach Compliance Code:unknown
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.82Is Samacsys:N
最长访问时间:5 ns其他特性:LINEAR/INTERLEAVED BURST SEQUENCE; INTERNALLY SELF-TIMED WRITE CYCLE; BYTE WRITE CONTROL
JESD-30 代码:R-PQFP-G100JESD-609代码:e0
长度:20 mm内存密度:4718592 bit
内存集成电路类型:ZBT SRAM内存宽度:18
功能数量:1端口数量:1
端子数量:100字数:262144 words
字数代码:256000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:256KX18输出特性:3-STATE
可输出:YES封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装形状:RECTANGULAR
封装形式:FLATPACK, LOW PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
座面最大高度:1.6 mm最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.65 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:14 mmBase Number Matches:1

MCM63Z818TQ100 数据手册

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Order this document  
by MCM63Z736/D  
SEMICONDUCTOR TECHNICAL DATA  
MCM63Z736  
MCM63Z818  
Advance Information  
128K x 36 and 256K x 18 Bit  
Pipelined ZBT RAM  
Synchronous Fast Static RAM  
The ZBT RAM is a 4M–bit synchronous fast static RAM designed to provide  
zero bus turnaround. The ZBT RAM allows 100% use of bus cycles during  
back–to–back read/write and write/read cycles. The MCM63Z736 is organized  
as128K wordsof36bitseachandtheMCM63Z818isorganizedas256Kwords  
of 18 bits each, fabricated with high performance silicon gate CMOS  
technology. This device integrates input registers, an output register, a 2–bit  
address counter, and high speed SRAM onto a single monolithic circuit for  
reduced parts count in communication applications. Synchronous design  
allows precise cycle control with the use of an external clock (CK). CMOS  
circuitry reduces the overall power consumption of the integrated functions for  
greater reliability.  
TQ PACKAGE  
TQFP  
CASE 983A–01  
Addresses (SA), data inputs (DQ), and all control signals except output enable  
(G) and linear burst order (LBO) are clock (CK) controlled through positive–  
edge–triggered noninverting registers.  
Write cycles are internally self–timed and are initiated by the rising edge of the  
clock (CK) input. This feature eliminates complex off–chip write pulse generation  
and provides increased timing flexibility for incoming signals.  
Forreadcycles, pipelinedSRAMoutputdataistemporarilystoredbyanedge–  
triggered output register and then released to the output buffers at the next rising  
edge of clock (CK).  
3.3 V LVTTL and LVCMOS Compatible  
MCM63Z736/MCM63Z818–133 = 4.2 ns Access/7.5 ns Cycle (133 MHz)  
MCM63Z736/MCM63Z818–100 = 5 ns Access/10 ns Cycle (100 MHz)  
Selectable Burst Sequencing Order (Linear/Interleaved)  
Internally Self–Timed Write Cycle  
Two–Cycle Deselect  
Byte Write Control  
ADV Controlled Burst  
100–Pin TQFP Package  
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc., and the architecture is supported by  
Micron Technology, Inc. and Motorola, Inc.  
This document contains information on a new product. Specifications and information herein are subject to change without notice.  
REV 1  
2/6/98  
Motorola, Inc. 1998  

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