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by MCM6246/D
SEMICONDUCTOR TECHNICAL DATA
MCM6246
512K x 8 Bit Static Random
Access Memory
The MCM6246 is a 4,194,304 bit static random access memory organized as
524,288 words of 8 bits. Static design eliminates the need for external clocks or
timing strobes, while CMOS circuitry reduces power consumption and provides
for greater reliability.
The MCM6246 is equipped with chip enable (E) and output enable (G) pins,
allowing for greater system flexibility and eliminating bus contention problems.
Either input, when high, will force the outputs into high impedance.
TheMCM6246isavailableina400mil, 36–leadsurface–mountSOJpackage.
WJ PACKAGE
400 MIL SOJ
CASE 893–01
PIN ASSIGNMENT
•
•
•
•
•
•
Single 5 V ± 10% Power Supply
Fast Access Time: 17/20/25/35 ns
Equal Address and Chip Enable Access Time
All Inputs and Outputs are TTL Compatible
Three–State Outputs
A
A
1
2
36
35
34
33
32
31
30
29
28
27
NC
A
A
A
3
4
A
A
Power Operation: 205/200/185/170 mA Maximum, Active AC
A
5
A
E
DQ
DQ
6
G
BLOCK DIAGRAM
7
DQ
DQ
V
8
A
A
V
9
CC
SS
V
10
V
CC
SS
A
A
DQ
11
12
26
25
DQ
DQ
DQ
MEMORY MATRIX
1024 ROWS x
4096 COLUMNS
A
A
A
A
ROW
DECODER
W
A
13
14
15
24
23
22
A
A
A
A
A
16
21
A
A
A
A
A
17
18
20
19
A
NC
COLUMN I/O
COLUMN DECODER
DQ
DQ
E
PIN NAMES
INPUT
DATA
CONTROL
A . . . . . . . . . . . . . . . . . . . Address Inputs
W . . . . . . . . . . . . . . . . . . . . Write Enable
G . . . . . . . . . . . . . . . . . . . Output Enable
E . . . . . . . . . . . . . . . . . . . . . . Chip Enable
DQ . . . . . . . . . . . . . . . Data Input/Output
NC . . . . . . . . . . . . . . . . . No Connection
A
A
A
A
A
A
A
A
A
DQ
DQ
V
CC
V
SS
. . . . . . . . . . . . + 5 V Power Supply
. . . . . . . . . . . . . . . . . . . . . . . Ground
W
G
REV 5
6/9/97
Motorola, Inc. 1997
MOTOROLA FAST SRAM
MCM6246
1