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MCM62486BFN19 PDF预览

MCM62486BFN19

更新时间： 2024-01-27 20:36:54
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA /
页数 文件大小 规格书
12页 201K
描述
32K x 9 Bit BurstRAM Synchronous Static RAM

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MCM62486BFN19 技术参数

生命周期：Obsolete零件包装代码：LCC
包装说明：QCCJ, LDCC44,.7SQ针数：44
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.32.00.41风险等级：5.81
最长访问时间：19 ns其他特性：OUTPUT BUFFER SUPPLY VOLTAGE 5V+/-10% OR 3.3V+/-10%; SELF-TIMED WRITE
I/O 类型：COMMONJESD-30 代码：S-PQCC-J44
JESD-609代码：e0内存密度：294912 bit
内存集成电路类型：CACHE SRAM内存宽度：9
功能数量：1端口数量：1
端子数量：44字数：32768 words
字数代码：32000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：32KX9输出特性：3-STATE
可输出：YES封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装等效代码：LDCC44,.7SQ
封装形状：SQUARE封装形式：CHIP CARRIER
并行/串行：PARALLEL电源：3.3/5,5 V
认证状态：Not Qualified最大待机电流：0.02 A
最小待机电流：4.5 V子类别：SRAMs
最大压摆率：0.15 mA最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：J BEND端子节距：1.27 mm
端子位置：QUAD

MCM62486BFN19 数据手册

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Order this document  
by MCM62486B/D  
SEMICONDUCTOR TECHNICAL DATA  
MCM62486B  
32K x 9 Bit BurstRAM  
Synchronous Static RAM  
With Burst Counter and Self–Timed Write  
The MCM62486B is a 294,912 bit synchronous static random access  
memory designed to provide a burstable, high–performance, secondary cache  
for the i486 and Pentium microprocessors. It is organized as 32,768 words of  
9 bits, fabricated with Motorola’s high–performance silicon–gate CMOS  
technology. The device integrates input registers, a 2–bit counter, high speed  
SRAM, and high drive capability outputs onto a single monolithic circuit for re-  
duced parts count implementation of cache data RAM applications. Synchro-  
nous design allows precise cycle control with the use of an external clock (K).  
CMOS circuitry reduces the overall power consumption of the integrated func-  
tions for greater reliability.  
FN PACKAGE  
44–LEAD PLCC  
CASE 777–01  
PIN ASSIGNMENT  
Addresses (A0 – A14), data inputs (D0 – D8), and all control signals except  
output enable (G) are clock (K) controlled through positive–edge–triggered  
noninverting registers.  
6
5
4
3
2
1
44 43 42 41 40  
39  
A11  
A12  
A13  
A14  
A2  
A3  
A4  
A5  
A6  
7
8
9
38  
37  
36  
35  
Bursts canbeinitiatedwitheitheraddressstatusprocessor(ADSP) or address  
status cache controller (ADSC) input pins. Subsequent burst addresses can be  
generated internally by the MCM62486B (burst sequence imitates that of the  
i486 and Pentium) and controlled by the burst address advance (ADV) input pin.  
The following pages provide more detailed information on burst controls.  
Write cycles are internally self–timed and are initiated by the rising edge of the  
clock (K) input. This feature eliminates complex off–chip write pulse generation  
and provides increased flexibility for incoming signals.  
The MCM62486B will be available in a 44–pin plastic leaded chip carrier  
(PLCC). Multiple power and ground pins have been utilized to minimize effects  
induced by output noise. Separate power and ground pins have been employed  
for DQ0 – DQ8 to allow user–controlled output levels of 5 volts or 3.3 volts.  
10  
11  
12  
13  
14  
15  
16  
17  
V
SS  
V
DQ7  
DQ6  
V
34  
33  
SS  
DQ0  
DQ1  
SSQ  
CCQ  
DQ2  
32  
31  
30  
29  
SSQ  
V
V
V
CCQ  
DQ5  
DQ4  
18 19 20 21 22 23 24 25 26 27 28  
•
•
Single 5 V ± 10% Power Supply (± 5% for MCM62486BFN11)  
PIN NAMES  
Choice of 5 V or 3.3 V ± 10% Power Supplies for Output Level  
Compatibility  
Fast Access Times:11/12/14/19 ns Max and Cycle Times:15/20/25 ns Min  
Internal Input Registers (Address, Data, Control)  
Internally Self–Timed Write Cycle  
ADSP, ADSC, and ADV Burst Control Pins  
Asynchronous Output Enable Controlled Three–State Outputs  
Common Data Inputs and Data Outputs  
High Output Drive Capability: 85 pF per I/O  
High Board Density PLCC Package  
A0 – A14 . . . . . . . . . . . . . . . . Address Inputs  
K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock  
W . . . . . . . . . . . . . . . . . . . . . . . . Write Enable  
G . . . . . . . . . . . . . . . . . . . . . . Output Enable  
S0, S1 . . . . . . . . . . . . . . . . . . . . Chip Selects  
ADV . . . . . . . . . . . . Burst Address Advance  
ADSP, ADSC . . . . . . . . . . . . Address Status  
DQ0 – DQ8 . . . . . . . . . . . Data Input/Output  
•
•
•
•
•
•
•
•
•
•
V
V
V
V
. . . . . . . . . . . . . . . . + 5 V Power Supply  
. . . . . . . Output Buffer Power Supply  
. . . . . . . . . . . . . . . . . . . . . . . . . . Ground  
. . . . . . . . . . . . Output Buffer Ground  
CC  
CCQ  
SS  
SSQ  
Fully TTL–Compatible  
Active High and Low Chip Select Inputs for Easy Depth Expansion  
All power supply and ground pins must be con-  
nectedfor proper operation of the device. V  
≥
CC  
V
CCQ  
at all times including power up.  
BurstRAM is a trademark of Motorola, Inc.  
i486 and Pentium are trademarks of Intel Corp.  
REV 2  
5/95  
Motorola, Inc. 1994  
1234567...12

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