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MCM6249WJ20 PDF预览

MCM6249WJ20

更新时间: 2024-09-24 22:14:03
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 存储
页数 文件大小 规格书
7页 120K
描述
1M x4 Bit Static Random Access Memory

MCM6249WJ20 数据手册

 浏览型号MCM6249WJ20的Datasheet PDF文件第2页浏览型号MCM6249WJ20的Datasheet PDF文件第3页浏览型号MCM6249WJ20的Datasheet PDF文件第4页浏览型号MCM6249WJ20的Datasheet PDF文件第5页浏览型号MCM6249WJ20的Datasheet PDF文件第6页浏览型号MCM6249WJ20的Datasheet PDF文件第7页 
Order this document  
by MCM6249/D  
SEMICONDUCTOR TECHNICAL DATA  
MCM6249  
1M x 4 Bit Static Random  
Access Memory  
The MCM6249 is a 4,194,304 bit static random access memory organized as  
1,048,576 words of 4 bits, fabricated using high–performance silicon–gate  
CMOS technology. Static design eliminates the need for external clocks or timing  
strobes, while CMOS circuitry reduces power consumption and provides for  
greater reliability.  
WJ PACKAGE  
400 MIL SOJ  
CASE 857A–02  
The MCM6249 is equipped with chip enable (E) and output enable (G) pins,  
allowing for greater system flexibility and eliminating bus contention problems.  
Either input, when high, will force the outputs into high impedance.  
TheMCM6249isavailableina400mil, 32–leadsurface–mountSOJpackage.  
PIN ASSIGNMENT  
A1  
Single 5 V ± 10% Power Supply  
Fast Access Time: 20/25/35 ns  
Equal Address and Chip Enable Access Time  
All Inputs and Outputs are TTL Compatible  
Three–State Outputs  
A7  
A8  
1
2
32  
31  
30  
29  
28  
27  
A0  
A5  
A9  
3
4
5
6
7
8
9
A4  
A17  
A6  
A19  
G
Power Operation: 190/175/160 mA Maximum, Active AC  
E
DQ3  
DQ0  
26  
25  
24  
23  
22  
21  
20  
19  
BLOCK DIAGRAM  
V
V
SS  
CC  
A13  
V
V
CC  
SS  
A12  
DQ2  
A2  
DQ1  
W
10  
A11  
A10  
11  
12  
A13  
A16  
13  
14  
15  
A15  
A14  
A3  
MEMORY MATRIX  
1024 ROWS x  
4096 COLUMNS  
A18  
A10  
A11  
A12  
A9  
A8  
A7  
A6  
ROW  
DECODER  
18  
17  
NC  
16  
A5  
A4  
PIN NAMES  
A0 – A19 . . . . . . . . . . . . Address Inputs  
W . . . . . . . . . . . . . . . . . . . . Write Enable  
G . . . . . . . . . . . . . . . . . . . Output Enable  
E . . . . . . . . . . . . . . . . . . . . . . Chip Enable  
DQ0 – DQ3 . . . . . . . . Data Input/Output  
NC . . . . . . . . . . . . . . . . . No Connection  
COLUMN I/O  
DQ0  
DQ3  
E
COLUMN DECODER  
INPUT  
DATA  
CONTROL  
V
CC  
V
SS  
. . . . . . . . . . . . + 5 V Power Supply  
. . . . . . . . . . . . . . . . . . . . . . . Ground  
A18 A17 A16 A15 A14 A19 A3 A2 A1  
A0  
DQ0  
DQ3  
W
G
REV 4  
5/95  
Motorola, Inc. 1995  

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