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MCM32A864SG33 PDF预览

MCM32A864SG33

更新时间: 2024-11-10 22:16:43
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 存储内存集成电路静态存储器
页数 文件大小 规格书
12页 172K
描述
128KB/256KB Secondary Cache Module With Tag, Valid, and Dirty for i486 Processor Systems

MCM32A864SG33 技术参数

生命周期:Obsolete包装说明:DIMM, DIMM112
Reach Compliance Code:unknownECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.84
Is Samacsys:N最长访问时间:25 ns
其他特性:BYTE WRITE; 16K X 10 CACHE TAG; 16K X 1 DIRTY BITI/O 类型:COMMON
JESD-30 代码:R-XDMA-N112内存密度:2097152 bit
内存集成电路类型:CACHE TAG SRAM MODULE内存宽度:32
功能数量:1端口数量:1
端子数量:112字数:65536 words
字数代码:64000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:64KX32输出特性:3-STATE
可输出:YES封装主体材料:UNSPECIFIED
封装代码:DIMM封装等效代码:DIMM112
封装形状:RECTANGULAR封装形式:MICROELECTRONIC ASSEMBLY
并行/串行:PARALLEL电源:5 V
认证状态:Not Qualified最大待机电流:0.2 A
最小待机电流:4.5 V子类别:SRAMs
最大压摆率:1.25 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:COMMERCIAL端子形式:NO LEAD
端子节距:1.27 mm端子位置:DUAL
Base Number Matches:1

MCM32A864SG33 数据手册

 浏览型号MCM32A864SG33的Datasheet PDF文件第2页浏览型号MCM32A864SG33的Datasheet PDF文件第3页浏览型号MCM32A864SG33的Datasheet PDF文件第4页浏览型号MCM32A864SG33的Datasheet PDF文件第5页浏览型号MCM32A864SG33的Datasheet PDF文件第6页浏览型号MCM32A864SG33的Datasheet PDF文件第7页 
Order this document  
by MCM32A732/D  
SEMICONDUCTOR TECHNICAL DATA  
MCM32A732  
MCM32A832  
MCM32A932  
MCM32A764  
MCM32A864  
MCM32A964  
Advance Information  
128KB/256KB Secondary Cache  
Module  
With Tag, Valid, and Dirty for i486  
Processor Systems  
This family of cache modules is well suited to provide the secondary cache for  
the Intel 82420 PCI chipset. This family provides the 128K Byte and 256K Byte  
cache sizes with valid, dirty and a choice of 7, 8, or 9 tag bits. The tag/valid bits  
have 12 ns access times for zero wait states at 33 MHz clock speeds. The PD  
pins map into the configuration register of the 82420 for auto–configuration of the  
cache controller during system startup.  
112–LEAD  
CARD EDGE  
CASE 1112–01  
TOP VIEW  
1
Low Profile Edge Connector: Burndy Part Number: CELP2X56SC3Z48  
Single 5 V ± 10% Power Supply  
All Inputs and Outputs are TTL Compatible  
Three State Outputs  
Fast Module Cycle Time: Up to External Processor Bus Speed of 33 MHz  
Cache Byte Write, Bank Chip Enable, Bank Output Enable  
Decoupling Capacitors are Used for Each Fast Static RAM  
High Quality Multi–Layer FR4 PWB With Separate Power and Ground Planes  
45  
46  
56  
BurstRAM is a registered trademark of Motorola.  
I486 is a registered trademark Intel Corp.  
This document contains information on a new product. Specifications and information herein are subject to change without notice.  
REV 1  
6/95  
Motorola, Inc. 1994  

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