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MCM32A864

更新时间: 2024-11-12 01:01:43
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA /
页数 文件大小 规格书
12页 172K
描述
128KB/256KB Secondary Cache Module

MCM32A864 数据手册

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Order this document  
by MCM32A732/D  
SEMICONDUCTOR TECHNICAL DATA  
MCM32A732  
MCM32A832  
MCM32A932  
MCM32A764  
MCM32A864  
MCM32A964  
Advance Information  
128KB/256KB Secondary Cache  
Module  
With Tag, Valid, and Dirty for i486  
Processor Systems  
This family of cache modules is well suited to provide the secondary cache for  
the Intel 82420 PCI chipset. This family provides the 128K Byte and 256K Byte  
cache sizes with valid, dirty and a choice of 7, 8, or 9 tag bits. The tag/valid bits  
have 12 ns access times for zero wait states at 33 MHz clock speeds. The PD  
pins map into the configuration register of the 82420 for auto–configuration of the  
cache controller during system startup.  
112–LEAD  
CARD EDGE  
CASE 1112–01  
TOP VIEW  
1
Low Profile Edge Connector: Burndy Part Number: CELP2X56SC3Z48  
Single 5 V ± 10% Power Supply  
All Inputs and Outputs are TTL Compatible  
Three State Outputs  
Fast Module Cycle Time: Up to External Processor Bus Speed of 33 MHz  
Cache Byte Write, Bank Chip Enable, Bank Output Enable  
Decoupling Capacitors are Used for Each Fast Static RAM  
High Quality Multi–Layer FR4 PWB With Separate Power and Ground Planes  
45  
46  
56  
BurstRAM is a registered trademark of Motorola.  
I486 is a registered trademark Intel Corp.  
This document contains information on a new product. Specifications and information herein are subject to change without notice.  
REV 1  
6/95  
Motorola, Inc. 1994  

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