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MCM218165BVT70R

更新时间： 2024-01-29 05:03:10
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 动态存储器光电二极管内存集成电路
页数 文件大小 规格书
28页 434K
描述
EDO DRAM, 1MX16, 70ns, CMOS, PDSO44, 0.400 INCH, TSOP2-50/44

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MCM218165BVT70R 技术参数

生命周期：Obsolete包装说明：TSOP2,
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.32.00.02风险等级：5.84
访问模式：FAST PAGE WITH EDO最长访问时间：70 ns
其他特性：RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESHJESD-30 代码：R-PDSO-G44
长度：20.955 mm内存密度：16777216 bit
内存集成电路类型：EDO DRAM内存宽度：16
功能数量：1端口数量：1
端子数量：44字数：1048576 words
字数代码：1000000工作模式：ASYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：1MX16输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：TSOP2
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE
认证状态：Not Qualified刷新周期：1024
座面最大高度：1.2 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子形式：GULL WING
端子节距：0.8 mm端子位置：DUAL
宽度：10.16 mmBase Number Matches：1

MCM218165BVT70R 数据手册

 浏览型号MCM218165BVT70R的Datasheet PDF文件第3页浏览型号MCM218165BVT70R的Datasheet PDF文件第4页浏览型号MCM218165BVT70R的Datasheet PDF文件第5页浏览型号MCM218165BVT70R的Datasheet PDF文件第7页浏览型号MCM218165BVT70R的Datasheet PDF文件第8页浏览型号MCM218165BVT70R的Datasheet PDF文件第9页 
AC OPERATING CONDITIONS AND CHARACTERISTICS  
(V  
= 3.3 V ± 0.3 V, T = 0 to 70°C, Unless Otherwise Noted)  
CC  
A
Input Timing Reference Level . . . . . . . . . . . VIH = 2.0 V, VIL = 0.8 V  
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V  
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ns  
Output Timing Reference Level . . . . . . . . VOL = 0.8 V, VOH = 2.0 V  
Output Load . . . . . . . . . . . . . . . . . . . . . . . . One TTL Load and 100 pF  
ALL DEVICES: READ, WRITE, READ–MODIFY–WRITE, AND REFRESH CYCLES (See Notes 1, 2, 3, 4, and 5)  
Symbol MCM218165BV–60 MCM218165BV–70  
Std  
Alt  
Min  
110  
40  
60  
10  
0
Max  
—
Min  
130  
50  
70  
12  
0
Max  
—
Parameter  
Random Read or Write Cycle Time  
RAS Precharge Time  
Unit Notes  
t
t
ns  
ns  
RELREL  
RC  
t
t
t
t
—
—
REHREL  
RELREH  
CELCEH  
RP  
RAS Pulse Width  
t
t
t
10 k  
10 k  
—
10 k  
10 k  
—
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ms  
ns  
ns  
ns  
ns  
ns  
6
7
RAS  
CAS  
ASR  
RAH  
LCAS/UCAS Pulse Width  
Row Address Setup Time  
Row Address Hold Time  
Column Address Setup Time  
Column Address Hold Time  
RAS to LCAS/UCAS Delay Time  
RAS to Column Address Delay Time  
Column Address to RAS Lead Time  
RAS Hold Time  
t
AVREL  
t
t
10  
0
—
10  
0
—
RELAX  
t
t
—
—
8
AVCEL  
ASC  
CAH  
RCD  
t
t
10  
20  
15  
30  
15  
60  
5
—
15  
20  
15  
35  
18  
70  
5
—
CELAX  
t
t
42  
30  
—
50  
35  
—
9
RELCEL  
t
t
10  
RELAV  
RAD  
t
t
AVREH  
RAL  
RSH  
CSH  
CRP  
t
t
t
t
t
t
—
—
CELREH  
RELCEH  
CEHREL  
LCAS/UCAS Hold Time  
—
—
LCAS/UCAS to RAS Precharge Time  
G to Data In Delay Time  
Transition Time (Rise and Fall)  
Refresh Period  
—
—
11  
12  
t
t
15  
1
—
18  
1
—
GLHDX  
GD  
t
T
t
T
50  
16  
—
50  
16  
—
t
t
—
0
—
0
RVRV  
REF  
CAS to Output in Low–Z  
Access Time from RAS  
t
t
t
t
CLZ  
CELQX  
RELQV  
CELQV  
t
—
—
—
—
60  
18  
30  
15  
—
—
—
—
70  
20  
35  
18  
13  
RAC  
CAC  
Access Time from LCAS/UCAS  
Access Time from Column Address  
Access Time from G  
t
14, 15  
15, 16  
t
t
AVQV  
AA  
t
t
GLQV  
GA  
NOTES:  
(continued)  
1. AC measurements assume t = 2.0 ns.  
T
2. An initial pause of 100 µs is required after power–up, followed by a minimum of initialization cycles (RAS–only refresh cycle or CAS before  
RAS refresh cycle). If the internal refresh counter is used, a minimum of eight CAS before RAS refresh cycles are required.  
3. In delayed write or read–modify–write cycles, G must disable the output buffer prior to applying data to the device.  
4. When both LCAS and UCAS go low at the same time, all 16 bits of data are written into the device. LCAS and UCAS can not be staggered  
within the same write/read cycles.  
5. All V  
and V  
pins will be supplied with the same voltages.  
SS  
CC  
6. t  
7. t  
8. t  
(min) = t  
(min) = t  
(min) + t  
(min) + t  
(min) + t in read–modify–write cycle.  
RAS  
CAS  
ASC  
RWD  
CWD  
RWL  
CWL  
T
(min) + t in read–modify–write cycle.  
T
(min), t  
(min), t  
(min), and t  
are determined by the earlier falling edge of LCAS or UCAS.  
RPC  
RCS  
WCS  
(max) limit ensures that t  
9. Operation within the t  
is greater than the specified t  
10. Operation within the t  
(max) can be met. t (max) is specified as a reference point only; if t  
RCD  
RAC  
RCD  
RCD  
RAD  
(max) limit, then access time is controlled exclusively by t .  
CAC  
RCD  
(max) limit ensures that t  
(max) can be met. t (max) is specified as a reference point only; if t  
RAD  
RAC  
RAD  
is greater than the specified t  
(max), then access time is controlled exclusively by t .  
AA  
RAD  
, and t  
11. t  
, t  
, t  
, t  
are determined by the latter rising edge of LCAS or UCAS.  
CRP CHR RCH CPA  
CPW  
12. V (min) and V (max) are reference levels for measuring timing or input signals. Transition times are measured between V and V  
.
IL  
IH  
IL  
IH  
13. Assumes that t  
≤ t  
RCD RCD  
(max) and t  
exceeds the value shown.  
≤ t  
(max). If t  
or t  
is greater than the maximum recommended value shown  
RAD  
RAD RAD  
RCD  
in this table, t  
RAC  
14. Assumes that t  
15. Access time is determined by the longer of t , t  
16. Assumes that t  
≥ t  
(max) and t  
≤ t  
(max).  
, t .  
RCD RCD  
RAD RAD  
AA CAC CPA  
≤ t  
(max) and t  
≥ t (max).  
RCD RCD  
RAD RAD  
MCM218165BV  
6
MOTOROLA DRAM  
1...3456789...28

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