Document Number: IMX6DQIEC
Rev. 6, 11/2018
NXP Semiconductors
Data Sheet: Technical Data
MCIMX6QxCxxxxC
MCIMX6QxCxxxxD
MCIMX6QxCxxxxE
MCIMX6DxCxxxxC
MCIMX6DxCxxxxD
MCIMX6DxCxxxxE
i.MX 6Dual/6Quad
ApplicationsProcessorsfor
Industrial Products
Package Information
FCPBGA Package
21 x 21 mm, 0.8 mm pitch
Ordering Information
See Table 1
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3 Signal Naming Convention . . . . . . . . . . . . . . . . . . . 7
Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Modules List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 Special Signal Considerations. . . . . . . . . . . . . . . . 17
3.2 Recommended Connections for Unused Analog
Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1 Introduction
The i.MX 6Dual/6Quad processors represent the latest
achievement in integrated multimedia applications
processors. These processors are part of a growing
family of multimedia-focused products that offer high
performance processing and are optimized for lowest
2
3
power consumption.
4
Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1 Chip-Level Conditions . . . . . . . . . . . . . . . . . . . . . . 18
4.2 Power Supplies Requirements and Restrictions . . 31
4.3 Integrated LDO Voltage Regulator Parameters . . 32
4.4 PLL Electrical Characteristics . . . . . . . . . . . . . . . . 34
4.5 On-Chip Oscillators . . . . . . . . . . . . . . . . . . . . . . . . 35
4.6 I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 36
4.7 I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 41
4.8 Output Buffer Impedance Parameters. . . . . . . . . . 45
4.9 System Modules Timing . . . . . . . . . . . . . . . . . . . . 48
4.10 Multi-Mode DDR Controller (MMDC). . . . . . . . . . . 60
4.11 General-Purpose Media Interface (GPMI) Timing. 60
4.12 External Peripheral Interface Parameters . . . . . . . 69
Boot Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . 130
5.1 Boot Mode Configuration Pins. . . . . . . . . . . . . . . 130
5.2 Boot Devices Interfaces Allocation . . . . . . . . . . . 131
Package Information and Contact Assignments. . . . . . 133
6.1 Signal Naming Convention . . . . . . . . . . . . . . . . . 133
6.2 21 x 21 mm Package Information . . . . . . . . . . . . 133
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
The i.MX 6Dual/6Quad processors feature advanced
®
®
implementation of the quad Arm Cortex -A9 core,
which operates at speeds up to 800 MHz. They include
2D and 3D graphics processors, 1080p video processing,
and integrated power management. Each processor
provides a 64-bit DDR3/DDR3L/LPDDR2-800 memory
interface and a number of other interfaces for connecting
®
peripherals, such as WLAN, Bluetooth , GPS, hard
drive, displays, and camera sensors.
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6
7
NXP Reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.