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MCF5270

更新时间: 2024-11-16 04:40:35
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飞思卡尔 - FREESCALE 控制器
页数 文件大小 规格书
56页 1096K
描述
32-bit Embedded Controller Division

MCF5270 数据手册

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MCF5271EC  
Rev. 1.2, 12/2004  
Freescale Semiconductor  
Hardware Specification  
MCF5271 Integrated  
Microprocessor  
Hardware Specification  
32-bit Embedded Controller Division  
Table of Contents  
The MCF5271 family is a highly integrated  
implementation of the ColdFire family of reduced  
®
1
2
3
4
5
6
7
8
9
MCF5271 Family Configurations..................... 2  
Block Diagram ................................................. 2  
Features .......................................................... 4  
Signal Descriptions........................................ 12  
Modes of Operation....................................... 16  
Design Recommendations ............................ 19  
Mechanicals/Pinouts and Part Numbers ....... 27  
Preliminary Electrical Characteristics............ 32  
Documentation .............................................. 55  
instruction set computing (RISC) microprocessors. This  
document describes pertinent features and functions of  
the MCF5271 family. The MCF5271 family includes the  
MCF5271 and MCF5270 microprocessors. The  
differences between these parts are summarized below in  
Table 1. This document is written from the perspective of  
the MCF5271 and unless otherwise noted, the  
information applies also to the MCF5270.  
The MCF5271 family combines low cost with high  
integration on the popular version 2 ColdFire core with  
over 96 (Dhrystone 2.1) MIPS at 100MHz. Positioned  
for applications requiring a cost-sensitive 32-bit  
solution, the MCF5271 family features a 10/100 Ethernet  
MAC and optional hardware encryption to ensure the  
application can be connected and protected. In addition,  
the MCF5271 family features an enhanced Multiply  
Accumulate Unit (eMAC), large on-chip memory (64  
Kbytes SRAM, 8 Kbytes configurable cache), and a  
32-bit SDR SDRAM memory controller.  
Technical Data  
© Freescale Semiconductor, Inc., 2004. All rights reserved.  

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