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MCC141537

更新时间： 2024-11-18 20:40:11
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 驱动接口集成电路
页数 文件大小 规格书
16页 161K
描述
Liquid Crystal Driver, 136-Segment, CMOS, DIE-182

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中文翻译

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MCC141537 技术参数

生命周期：Obsolete零件包装代码：DIE
包装说明：DIE,针数：182
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.84
数据输入模式：PARALLEL显示模式：DOT MATRIX
输入特性：STANDARD接口集成电路类型：LIQUID CRYSTAL DISPLAY DRIVER
JESD-30 代码：R-XUUC-N182复用显示功能：YES
功能数量：1区段数：136
端子数量：182最高工作温度：85 °C
最低工作温度：-30 °C输出特性：TOTEM-POLE
封装主体材料：UNSPECIFIED封装代码：DIE
封装形状：RECTANGULAR封装形式：UNCASED CHIP
认证状态：Not Qualified最大压摆率：0.3 mA
最大供电电压：3.5 V最小供电电压：2.4 V
标称供电电压：3 V电源电压1-最大：3.5 V
电源电压1-分钟：2.4 V表面贴装：YES
技术：CMOS温度等级：OTHER
端子形式：NO LEAD端子位置：UPPER
最小 fmax：1 MHzBase Number Matches：1

MCC141537 数据手册

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Order this document  
by MCM64PE32/D  
SEMICONDUCTOR TECHNICAL DATA  
MCM64PE32  
MCM64PE64  
Advance Information  
256K/512K Pipelined BurstRAM  
Secondary Cache Module  
for Pentium  
160–LEAD CARD EDGE  
CASE TBD  
TOP VIEW  
1
The MCM64PE32 (256K) and MCM64PE64 (512K) are designed to provide  
a burstable, high performance, L2 cache for the Pentium microprocessor in  
conjunction with Intel’s Triton II chip set. The MCM64PE32 is configured as 32K  
x 64 bits and the MCM64PE64 is configured as 64K x 64 bits. Both are packaged  
in a 160 pin card edge memory module. The MCM64PE32 module uses  
Motorola’s 3.3 V 32K x 32 BurstRAMs and one Motorola 5 V 32K x 8 FSRAM for  
the tag RAM. The MCM64PE64 module uses Motorola’s 3.3 V 64K x 32  
BurstRAMs and one Motorola 5 V 32K x 8 FSRAM for the tag RAM.  
Bursts can be initiated with either address status processor (ADSP) or cache  
address status (CADS). Subsequent burst addresses are generated internal to  
the BurstRAM by the cache burst advance (CADV) input pin.  
Write cycles are internally self timed and are initiated by the rising edge of the  
clock (CLK0) input. Eight write enables are provided for byte write control.  
PD0 – PD3 map into the Triton II chip set for auto–configuration of the cache  
control.  
42  
43  
•
•
•
•
•
•
•
•
•
Pentium–Style Burst Counter on Chip  
Pipelined Data Out  
160 Pin Card Edge Module  
Address Pipeline Supported by ADSP Disabled with Ex  
All Cache Data and Tag I/Os are TTL Compatible  
Three State Outputs  
Byte Write Capability  
Fast Module Clock Rate: 66 MHz  
Fast SRAM Access Times:15 ns for Tag RAM  
8 ns for Data RAMs  
•
•
•
One–Cycle Deselect Data RAMs  
Decoupling Capacitors for Each Fast Static RAM  
High Quality Multi–Layer FR4 PWB with Separate Power and Ground  
Planes  
80  
•
•
8 Bits Tag RAM  
Dual Power Supplies: 3.3 V + 10%, – 5%  
5 V ± 10%  
•
•
•
Burndy Connector, Part Number: CELP2X80SC3Z48  
Intel COAST 3.0 Option III Compliant  
Burst Order Select (BOSEL) Option  
BurstRAM is a trademark of Motorola.  
Mfax is a trademark of Motorola.  
Pentium is a trademark of Intel Corp.  
This document contains information on a new product. Motorola reserves the right to change or discontinue this product without notice.  
12/9/96  
Motorola, Inc. 1996  
1234567...16

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