MC88PL117FN

更新时间： 2024-09-16 22:46:19

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		时钟驱动器逻辑集成电路
页数	文件大小	规格书
11页	143K
描述
CMOS PLL CLOCK DRIVER

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技术参数
数据手册

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MC88PL117FN 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	LCC	包装说明：	QCCJ, LDCC52,.8SQ
针数：	52	Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01	风险等级：	5.85
Is Samacsys：	N	其他特性：	O/P FREQUENCY RATIOS ARE 0.33F/0.5F/0.66F/1.0F/1.33F/1.5F/2.0F/3.0F/4.0F/6.0F/8.0F
系列：	88PL	输入调节：	MUX
JESD-30 代码：	S-PQCC-J52	JESD-609代码：	e0
长度：	19.1262 mm	逻辑集成电路类型：	PLL BASED CLOCK DRIVER
功能数量：	1	反相输出次数：
端子数量：	52	实输出次数：	15
最高工作温度：	70 °C	最低工作温度：
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ	封装等效代码：	LDCC52,.8SQ
封装形状：	SQUARE	封装形式：	CHIP CARRIER
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	5 V
认证状态：	Not Qualified	Same Edge Skew-Max（tskwd）：	0.5 ns
座面最大高度：	4.57 mm	子类别：	Clock Drivers
最大供电电压 (Vsup)：	5.25 V	最小供电电压 (Vsup)：	4.75 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	19.1262 mm
最小 fmax：	80 MHz	Base Number Matches：	1

MC88PL117FN 数据手册

SEMICONDUCTOR TECHNICAL DATA

The MC88PL117 utilizes proven phase–locked loop clock driver

technology to create a large fan–out, multiple frequency and phase, low

skew clock driver. The 88PL117 provides the clock frequencies

necessary to drive systems using the PowerPC 601 microprocessor

and the Pentium microprocessor (see applications section for details).

A total of 14 high current, matched impedance outputs are available in 8

programmable output frequency and phase configurations. Output

frequencies are referenced to a system frequency, Q, and are available at

2X, 1X, and 1/2X the Q frequency. Four programmable input frequency

multiplication ratios can be programmed to provide outputs at 1X, 2X, and

4X the system frequency Q. Details on the programmable configurations

can be found in the applications section of this data sheet.

CMOS PLL

CLOCK DRIVER

• Clock Driver for PowerPC 601 and Pentium Microprocessors

• 14 programmable outputs

• Maximum output–to–output skew of 500ps for a single frequency

• Maximum output–to–output skew of 500ps for multiple frequencies

• f

MAX

of 2X_Q = 120MHz

• One output with programmable phase capability

FN SUFFIX

52–LEAD PLASTIC LEADLESS

CHIP CARRIER (PLCC)

CASE 778–02

• ±36mA DC current outputs drive 50Ω transmission lines

• A lock indicator output (LOCK) goes high when steady–state

phase–lock is achieved

• OE/MR 3–state control

• Dedicated feedback output

• Two selectable clock inputs

• PLL enable pin for testability

• Dynamic Switch Between SYNC Inputs

One output (QFEED) is dedicated for feedback. It is located physically close to the FEEDBACK input pin to minimize the

feedback line length. External delay (increased wire length) or logic can be inserted in the feedback path if necessary. Proper

termination of the feedback line is necessary for any line length over one inch.

One output is provided with up to eight selectable 1/8 or 1/4 period (45° or 90°) delay increments. Three control pins, 2,

and 0, program the eight increments; the increment/phase shift positions are shown in Table 3. in the applications section.

All outputs can be 3–stated (high impedance) during board–level testing with the OE/MR pin; the QFEED and LOCK outputs

will not be 3–stated, which allows the 88PL117 to remain in a phase–locked condition. Correct phase and frequency coherency

will be guaranteed one to two cycles after bringing the OE/MR pin high. The PLL_EN pin disables the PLL and gates the SYNC

input signal directly into the internal clock distribution network to provide low frequency testability. Two selectable SYNC inputs

(SYNC0 and SYNC1) are provided for clock redundancy or ease of testability. The device is guaranteed to lock to the new SYNC

input when the REF_SEL input is switched dynamically.

A phase–lock indicator output (LOCK) stays low when the part is out of lock (start–up, etc.) and goes high when steady–state

phase–lock is achieved. The lock indicator circuitry works reliably for VCO frequencies down to 55MHz. For VCO frequencies

less than 55MHz, no guarantees are offered for the lock indicator output.

The MC88PL117 VCO is capable of operating at frequencies higher than the output divider and feedback structures are able

to follow. When the VCO is in the mode described above, it is referred to as “runaway” and the device will not lock. The condition

usually occurs at power–up. To avoid runaway, it is recommended that the device be fully powered before a sync signal is

applied.

PowerPC is a trademark of International Business Machines Corporation.

1/97

REV 4

Motorola, Inc. 1997

12 3 4 5 6 7...11

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MC8F1-8.000MHZ	CALIBER	获取价格	Parallel - Fundamental Quartz Crystal, 8MHz Nom, SMD, 2 PIN

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