Datasheet > MC88LV926EG

MC88LV926EG

更新时间： 2024-09-17 20:03:39

品牌	Logo	应用领域
艾迪悌 - IDT		驱动光电二极管逻辑集成电路
页数	文件大小	规格书
11页	294K
描述
PLL Based Clock Driver, 88LV Series, 4 True Output(s), 1 Inverted Output(s), CMOS, PDSO20, LEAD FREE, PLASTIC, SOIC-20

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MC88LV926EG 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	SOIC	包装说明：	LEAD FREE, PLASTIC, SOIC-20
针数：	20	Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01	风险等级：	5.75
系列：	88LV	输入调节：	STANDARD
JESD-30 代码：	R-PDSO-G20	JESD-609代码：	e3
长度：	12.8 mm	逻辑集成电路类型：	PLL BASED CLOCK DRIVER
最大I（ol）：	0.024 A	湿度敏感等级：	1
功能数量：	1	反相输出次数：	1
端子数量：	20	实输出次数：	4
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装等效代码：	SOP20,.4	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	峰值回流温度（摄氏度）：	260
电源：	3.3 V	传播延迟（tpd）：	13.5 ns
认证状态：	Not Qualified	Same Edge Skew-Max（tskwd）：	0.75 ns
座面最大高度：	2.65 mm	子类别：	Clock Drivers
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Matte Tin (Sn) - annealed	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	30	宽度：	7.5 mm
最小 fmax：	66 MHz	Base Number Matches：	1

MC88LV926EG 数据手册

DATA SHEET

Rev. 7, 4/2006

Document Number: MC88LV926

Freescale Semiconductor

Technical Data

MC88LV926

Low Skew CMOS PLL 68060 Clock

Low Skew CMOS PLL 68060

Driver

MC88LV926

Clock Driver

The MC88LV926 Clock Driver utilizes phase-locked loop technology to lock its

low skew outputs' frequency and phase onto an input reference clock. It is

designed to provide clock distribution for CISC microprocessor or single

processor RISC systems. The RST_IN/RST_OUT(LOCK) pins provide a

processor reset function designed specifically for the MC68/EC/LC030/040/060

microprocessor family. To support the 68060 processor, the 88LV926 operates

from a 3.3 V supply.

LOW SKEW CMOS PLL

68080 CLOCK DRIVER

The PLL allows the high current, low skew outputs to lock onto a single clock

input and distribute it to multiple locations on a board. The PLL also allows the

MC88LV926 to multiply a low frequency input clock and distribute it locally at a

higher (2X) system frequency.

Features

DW SUFFIX

20-LEAD PLASTIC SOIC PACKAGE

CASE 751D-06

•

2X_Q Output Meets All Requirements of the 50 and 66 MHz 68060

Microprocessor PCLK Input Specifications

•

Low Voltage 3.3 V V_CC

Three Outputs (Q0–Q2) with Output–Output Skew <500 ps

CLKEN Output for Half Speed Bus Applications

The Phase Variation from Part-to-Part Between SYNC and the ‘Q' Outputs Is

Less than 600 ps (Derived from the T_PDSpecification, Which Defines the

Part-to-Part Skew)

EG SUFFIX

20-LEAD PLASTIC SOIC PACKAGE

Pb-FREE PACKAGE

•

SYNC Input Frequency Range from 5.0 MHz to 2X_Q F_Max/4

All Outputs Have ± 36 mA Drive (Equal High and Low) CMOS Levels

Can Drive Either CMOS or TTL Inputs. All Inputs Are TTL-Level Compatible

with V_CC= 3.3 V

CASE 751D-06

•

Test Mode Pin (PLL_EN) Provided for Low Frequency Testing

20-Lead SOIC Pb-Free Package Available

Three ‘Q' outputs (Q0-Q2) are provided with less than 500 ps skew between their rising edges. A 2X_Q output runs at twice

the ‘Q' output frequency. The 2X_Q output is ideal for 68060 systems which require a 2X processor clock input, and it meets the

tight duty cycle spec of the 50 and 66 MHz 68060. The QCLKEN output is designed to drive the CLKEN input of the 68060 when

the bus logic runs at half of the microprocessor clock rate. The QCLKEN output is skewed relative to the 2X_Q output to ensure

that CLKEN setup and hold times of the 68060 are satisfied. A Q/2 frequency is fed back internally, providing a fixed 2X

multiplication from the ‘Q' outputs to the SYNC input. Since the feedback is done internally (no external feedback pin is provided)

the input/output frequency relationships are fixed. The Q3 output provides an inverted clock output to allow flexibility in the clock

tree design.

In normal phase-locked operation the PLL_EN pin is held high. Pulling the PLL_EN pin low disables the VCO and puts the

88LV926 in a static ‘test mode'. In this mode there is no frequency limitation on the input clock, which is necessary for a low

frequency board test environment.

The RST_OUT(LOCK) pin doubles as a phase-lock indicator. When the RST_IN pin is held high, the open drain RST_OUT

pin will be pulled actively low until phase-lock is achieved. When phase-lock occurs, the RST_OUT(LOCK) is released and a pull-

up resistor will pull the signal high. To give a processor reset signal, the RST_IN pin is toggled low, and the RST_OUT(LOCK)

pin will stay low for 1024 cycles of the ‘Q' output frequency after the RST_IN pin is brought back high.

Description of the RST_IN/RST_OUT(LOCK) Functionality

The RST_IN and RST_OUT(LOCK) pins provide a 68030/040/060 processor reset function, with the RST_OUT pin also acting

as a lock indicator. If the RST_IN pin is held high during system power-up, the RST_OUT pin will be in the low state until steady

state phase/frequency lock to the input reference is achieved. 1024 ‘Q' output cycles after phase-lock is achieved the

RST_OUT(LOCK) pin will go into a high impedance state, allowing it to be pulled high by an external pull-up resistor (see the AC/

DC specs for the characteristics of the RST_OUT(LOCK) pin). If the RST_IN pin is held low during power-up, the

RST_OUT(LOCK) pin will remain low.

IDT™ Low Skew CMOS PLL 68060 Clock Driver

MC88LV926

Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc

12 3 4 5 6 7...11

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与MC88LV926EG相关器件

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