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MC74VHCT74A_09

更新时间： 2024-11-29 12:22:51
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安森美 - ONSEMI 触发器
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6页 156K
描述
Dual D-Type Flip-Flop with Set and Reset

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MC74VHCT74A_09 数据手册

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MC74VHCT74A  
Dual D-Type Flip-Flop  
with Set and Reset  
The MC74VHCT74A is an advanced high speed CMOS D−type  
flip−flop fabricated with silicon gate CMOS technology. It achieves  
high speed operation similar to equivalent Bipolar Schottky TTL  
while maintaining CMOS low power dissipation.  
The signal level applied to the D input is transferred to Q output  
during the positive going transition of the Clock pulse.  
http://onsemi.com  
MARKING DIAGRAMS  
Reset (RD) and Set (SD) are independent of the Clock (CP) and are  
accomplished by setting the appropriate input Low.  
The internal circuit is composed of three stages, including a buffer  
output which provides high noise immunity and stable output. The  
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V  
systems to 3.0 V systems.  
The VHCT inputs are compatible with TTL levels. This device can  
be used as a level converter for interfacing 3.3 V to 5.0 V, because it  
has full 5.0 V CMOS level output swings.  
The VHCT74A input structures provide protection when voltages  
between 0 V and 5.5 V are applied, regardless of the supply voltage.  
14  
SOIC−14  
D SUFFIX  
CASE 751A  
VHCT74AG  
AWLYWW  
1
1
14  
1
VHCT  
74A  
TSSOP−14  
DT SUFFIX  
CASE 948G  
ALYWG  
1
G
A
= Assembly Location  
WL, L = Wafer Lot  
= Year  
The output structures also provide protection when V = 0 V. These  
CC  
Y
input and output structures help prevent device destruction caused by  
supply voltage − input/output voltage mismatch, battery backup, hot  
insertion, etc.  
WW, W = Work Week  
G or G = Pb−Free Package  
(Note: Microdot may be in either location)  
Features  
RD1  
D1  
1
2
14  
13 RD2  
12  
V
CC  
• High Speed: f  
= 60 MHz (Typ) at V = 5.0 V  
CC  
max  
• Low Power Dissipation: I = 2 mA (Max) at T = 25°C  
CC  
A
3
4
CP1  
SD1  
D2  
• Power Down Protection Provided on Inputs  
11 CP2  
10 SD2  
• Balanced Propagation Delays  
Q1  
Q1  
5
6
7
• Designed for 4.5 V to 5.5 V Operating Range  
9
8
Q2  
Q2  
• Low Noise: V  
= 0.8 V (Max)  
OLP  
GND  
• Pin and Function Compatible with Other Standard Logic Families  
• Latchup Performance Exceeds 300 mA  
Figure 1. Pin Assignment  
FUNCTION TABLE  
• ESD Performance: HBM > 2000 V; Machine Model > 200 V  
• Chip Complexity: 128 FETs or 32 Equivalent Gates  
• Pb−Free Packages are Available  
Inputs  
Outputs  
SD  
RD  
CP  
D
Q
Q
L
H
L
H
H
H
H
H
H
L
L
H
H
H
H
H
X
X
X
X
X
X
H
L
X
X
X
H
L
H*  
H
L
L
H
H*  
L
13  
12  
11  
10  
1
2
3
4
RD1  
D1  
RD2  
D2  
9
8
5
6
H
Q2  
Q2  
Q1  
Q1  
L
H
No Change  
No Change  
No Change  
CP1  
SD1  
CP2  
SD2  
*Both outputs will remain high as long as Set and Reset  
are low, but the output states are unpredictable if Set  
and Reset go high simultaneously.  
Figure 2. Logic Diagram  
ORDERING INFORMATION  
See detailed ordering and shipping information on page 3 of  
this data sheet.  
© Semiconductor Components Industries, LLC, 2009  
1
Publication Order Number:  
November, 2009 − Rev. 6  
MC74VHCT74A/D  
123456

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