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MC74VHCU04D PDF预览

MC74VHCU04D

更新时间: 2024-10-01 23:05:47
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
5页 141K
描述
Hex Inverter

MC74VHCU04D 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP14,.25
针数:14Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.1
系列:AHC/VHCJESD-30 代码:R-PDSO-G14
JESD-609代码:e0长度:8.65 mm
负载电容(CL):50 pF逻辑集成电路类型:INVERTER
最大I(ol):0.008 A湿度敏感等级:1
功能数量:6输入次数:1
端子数量:14最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:2/5.5 V
Prop。Delay @ Nom-Sup:8 ns传播延迟(tpd):13 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:1.75 mm子类别:Gates
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3.9 mm
Base Number Matches:1

MC74VHCU04D 数据手册

 浏览型号MC74VHCU04D的Datasheet PDF文件第2页浏览型号MC74VHCU04D的Datasheet PDF文件第3页浏览型号MC74VHCU04D的Datasheet PDF文件第4页浏览型号MC74VHCU04D的Datasheet PDF文件第5页 
SEMICONDUCTOR TECHNICAL DATA  
The MC74VHCU04 is an advanced high speed CMOS unbuffered inverter  
fabricated with silicon gate CMOS technology. It achieves high speed  
operation similar to equivalent Bipolar Schottky TTL while maintaining  
CMOS low power dissipation.  
The inputs tolerate voltages up to 7V, allowing the interface of 5V systems  
to 3V systems.  
D SUFFIX  
14–LEAD SOIC PACKAGE  
CASE 751A–03  
High Speed: t  
= 3.5ns (Typ) at V  
= 5V  
PD  
Low Power Dissipation: I  
CC  
= 2µA (Max) at T = 25°C  
CC  
A
High Noise Immunity: V  
Power Down Protection Provided on Inputs  
Balanced Propagation Delays  
= V  
= 10% V (Min.)  
NIH  
NIL  
CC  
DT SUFFIX  
14–LEAD TSSOP PACKAGE  
CASE 948G–01  
Designed for 2V to 5.5V Operating Range  
Low Noise: V  
= 0.8V (Max)  
OLP  
Pin and Function Compatible with Other Standard Logic Families  
Latchup Performance Exceeds 300mA  
ESD Performance: HBM > 2000V; Machine Model > 200V  
Chip Complexity: 12 FETs or 3 Equivalent Gates  
M SUFFIX  
14–LEAD SOIC EIAJ PACKAGE  
CASE 965–01  
LOGIC DIAGRAM  
1
3
2
4
ORDERING INFORMATION  
A1  
A2  
A3  
Y1  
Y2  
Y3  
MC74VHCUXXD  
MC74VHCUXXDT TSSOP  
MC74VHCUXXM SOIC EIAJ  
SOIC  
5
6
8
FUNCTION TABLE  
Y = A  
Inputs  
A
Outputs  
Y
9
A4  
A5  
A6  
Y4  
Y5  
Y6  
L
H
L
11  
13  
10  
12  
H
Pinout: 14–Lead Packages (Top View)  
V
A6  
13  
Y6  
12  
A5  
11  
Y5  
10  
A4  
9
Y4  
8
CC  
14  
1
2
3
4
5
6
7
A1  
Y1  
A2  
Y2  
A3  
Y3  
GND  
6/97  
REV 0  
Motorola, Inc. 1997  

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