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MC74VHCT86ADTR2G PDF预览

MC74VHCT86ADTR2G

更新时间: 2024-10-01 01:11:27
品牌 Logo 应用领域
安森美 - ONSEMI 光电二极管逻辑集成电路石英晶振触发器
页数 文件大小 规格书
6页 87K
描述
Quad 2-Input XOR Gate / CMOS Logic Level Shifter

MC74VHCT86ADTR2G 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP, TSSOP14,.25针数:14
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:0.83系列:AHCT/VHCT
JESD-30 代码:R-PDSO-G14JESD-609代码:e4
长度:5 mm负载电容(CL):50 pF
逻辑集成电路类型:XOR GATE最大I(ol):0.008 A
湿度敏感等级:1功能数量:4
输入次数:2端子数量:14
最高工作温度:85 °C最低工作温度:-55 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP14,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:5 V
Prop。Delay @ Nom-Sup:10 ns传播延迟(tpd):16.5 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:1.2 mm子类别:Gates
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:OTHER
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40宽度:4.4 mm
Base Number Matches:1

MC74VHCT86ADTR2G 数据手册

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MC74VHCT86A  
Quad 2-Input XOR Gate /  
CMOS Logic Level Shifter  
with LSTTL−Compatible Inputs  
The MC74VHCT86A is an advanced high speed CMOS 2−input  
Exclusive−OR gate fabricated with silicon gate CMOS technology. It  
achieves high speed operation similar to equivalent Bipolar Schottky  
TTL while maintaining CMOS low power dissipation.  
http://onsemi.com  
The internal circuit is composed of three stages, including a buffer  
output which provides high noise immunity and stable output.  
The device input is compatible with TTL−type input thresholds and  
the output has a full 5 V CMOS level output swing. The input  
protection circuitry on this device allows overvoltage tolerance on the  
input, allowing the device to be used as a logic−level translator from  
3.0 V CMOS logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic  
to 3.0 V CMOS Logic while operating at the high−voltage power  
supply.  
14−LEAD SOIC  
D SUFFIX  
CASE 751A  
14−LEAD TSSOP  
DT SUFFIX  
CASE 948G  
PIN CONNECTION AND  
MARKING DIAGRAM (Top View)  
The MC74VHCT86A input structure provides protection when  
voltages up to 7 V are applied, regardless of the supply voltage. This  
allows it to be used to interface 5 V circuits to 3 V circuits. The output  
V
B4  
13  
A4  
12  
Y4  
11  
B3  
10  
A3  
9
Y3  
8
CC  
14  
structures also provide protection when V = 0 V. These input and  
CC  
output structures help prevent device destruction caused by supply  
voltage − input/output voltage mismatch, battery backup, hot  
insertion, etc.  
1
2
3
4
5
6
7
High Speed: t = 4.8 ns (Typ) at V = 5 V  
PD  
CC  
A1  
B1  
Y1  
A2  
B2  
Y2 GND  
Low Power Dissipation: I = 2 mA (Max) at T = 25°C  
CC  
A
For detailed package marking information, see the Marking  
Diagram section on page 4 of this data sheet.  
TTL−Compatible Inputs: V = 0.8 V; V = 2.0 V  
IL  
IH  
Power Down Protection Provided on Inputs and Outputs  
Balanced Propagation Delays  
FUNCTION TABLE  
Designed for 2 V to 5.5 V Operating Range  
Inputs  
Output  
Y
Low Noise: V  
= 0.8 V (Max)  
OLP  
A
B
Pin and Function Compatible with Other Standard Logic Families  
Latchup Performance Exceeds 300 mA  
L
L
L
H
L
L
H
H
L
ESD Performance: HBM > 2000 V; Machine Model > 200 V  
These Devices are Pb−Free and are RoHS Compliant  
H
H
H
LOGIC DIAGRAM  
ORDERING INFORMATION  
1
A1  
3
Device  
MC74VHCT86ADR2G  
Package  
Shipping  
Y1  
2
B1  
4
A2  
SOIC−14 2500 / Tape &  
(Pb−Free) Reel  
6
Y2  
5
B2  
MC74VHCT86ADTR2G TSSOP−14 2500 / Tape &  
(Pb−Free) Reel  
Y = A)B  
9
A3  
8
Y3  
10  
B3  
12  
A4  
11  
Y4  
13  
B4  
© Semiconductor Components Industries, LLC, 2014  
1
Publication Order Number:  
November, 2014 − Rev. 3  
MC74VHCT86A/D  

MC74VHCT86ADTR2G 替代型号

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