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MC74VHCT240ADWR2 PDF预览

MC74VHCT240ADWR2

更新时间: 2024-11-04 14:53:15
品牌 Logo 应用领域
安森美 - ONSEMI 驱动光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
6页 98K
描述
AHCT/VHCT SERIES, DUAL 4-BIT DRIVER, INVERTED OUTPUT, PDSO20, SOIC-20

MC74VHCT240ADWR2 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP20,.4
针数:20Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.24
Is Samacsys:N控制类型:ENABLE LOW
系列:AHCT/VHCTJESD-30 代码:R-PDSO-G20
JESD-609代码:e0长度:12.8 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.008 A湿度敏感等级:1
位数:4功能数量:2
端口数量:2端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:INVERTED
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP20,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TAPE AND REEL
峰值回流温度(摄氏度):240电源:5 V
Prop。Delay @ Nom-Sup:10 ns传播延迟(tpd):10 ns
认证状态:Not Qualified座面最大高度:2.65 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:7.5 mmBase Number Matches:1

MC74VHCT240ADWR2 数据手册

 浏览型号MC74VHCT240ADWR2的Datasheet PDF文件第2页浏览型号MC74VHCT240ADWR2的Datasheet PDF文件第3页浏览型号MC74VHCT240ADWR2的Datasheet PDF文件第4页浏览型号MC74VHCT240ADWR2的Datasheet PDF文件第5页浏览型号MC74VHCT240ADWR2的Datasheet PDF文件第6页 
MC74VHCT240A  
Octal Bus Buffer/Line Driver  
Inverting with 3−State Outputs  
The MC74VHCT240A is an advanced high speed CMOS octal bus  
buffer fabricated with silicon gate CMOS technology. It achieves high  
speed operation similar to equivalent Bipolar Schottky TTL while  
maintaining CMOS low power dissipation.  
http://onsemi.com  
The MC74VHCT240A is an inverting 3−state buffer, and has two  
active−low output enables. This device is designed to be used with  
3−state memory address drivers, etc.  
MARKING  
DIAGRAMS  
The VHCT inputs are compatible with TTL levels. This device can  
be used as a level converter for interfacing 3.3 V to 5.0 V, because it  
has full 5.0 V CMOS level output swings.  
The VHCT240A input and output (when disabled) structures  
provide protection when voltages between 0 V and 5.5 V are applied,  
regardless of the supply voltage. These input and output structures  
help prevent device destruction caused by supply  
voltage−input/output voltage mismatch, battery backup, hot insertion,  
etc.  
20  
1
VHCT240A  
AWLYYWWG  
SOIC−20WB  
SUFFIX DW  
CASE 751D  
1
20  
VHCT  
240A  
ALYWG  
G
Features  
High Speed: t = 5.6 ns (Typ) at V = 5.0 V  
PD  
CC  
1
TSSOP−20  
SUFFIX DT  
CASE 948E  
Low Power Dissipation: I = 4 mA (Max) at T = 25°C  
CC  
A
1
TTL−Compatible Inputs: V = 0.8 V; V = 2.0 V  
IL  
IH  
Power Down Protection Provided on Inputs and Outputs  
Balanced Propagation Delays  
A
= Assembly Location  
= Wafer Lot  
WL, L  
YY, Y  
= Year  
Designed for 4.5 V to 5.5 V Operating Range  
Low Noise: V  
WW, W = Work Week  
G or G  
= 1.1 V (Max)  
OLP  
= Pb−Free Package  
(Note: Microdot may be in either location)  
Pin and Function Compatible with Other Standard Logic Families  
Latchup Performance Exceeds 300 mA  
ESD Performance:  
Human Body Model > 2000 V;  
Machine Model > 200 V  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 4 of this data sheet.  
Chip Complexity: 110 FETs or 27.5 Equivalent Gates  
These Devices are Pb−Free and are RoHS Compliant  
© Semiconductor Components Industries, LLC, 2014  
1
Publication Order Number:  
October, 2014 − Rev. 7  
MC74VHCT240A/D  

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