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MC74VHCT240AMR2 PDF预览

MC74VHCT240AMR2

更新时间: 2024-02-16 13:21:10
品牌 Logo 应用领域
安森美 - ONSEMI 驱动光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
8页 94K
描述
AHCT/VHCT SERIES, DUAL 4-BIT DRIVER, INVERTED OUTPUT, PDSO20, EIAJ, SOIC-20

MC74VHCT240AMR2 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP,
针数:20Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.61
系列:AHCT/VHCTJESD-30 代码:R-PDSO-G20
JESD-609代码:e0长度:12.575 mm
逻辑集成电路类型:BUS DRIVER位数:4
功能数量:2端口数量:2
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):NOT SPECIFIED
传播延迟(tpd):10 ns认证状态:Not Qualified
座面最大高度:2.05 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:5.275 mmBase Number Matches:1

MC74VHCT240AMR2 数据手册

 浏览型号MC74VHCT240AMR2的Datasheet PDF文件第2页浏览型号MC74VHCT240AMR2的Datasheet PDF文件第3页浏览型号MC74VHCT240AMR2的Datasheet PDF文件第4页浏览型号MC74VHCT240AMR2的Datasheet PDF文件第5页浏览型号MC74VHCT240AMR2的Datasheet PDF文件第6页浏览型号MC74VHCT240AMR2的Datasheet PDF文件第7页 
ON Semiconductort  
Octal Bus Buffer/Line Driver  
Inverting with 3-State Outputs  
MC74VHCT240A  
The MC74VHCT240A is an advanced high speed CMOS octal bus  
buffer fabricated with silicon gate CMOS technology. It achieves high  
speed operation similar to equivalent Bipolar Schottky TTL while  
maintaining CMOS low power dissipation.  
DW SUFFIX  
20–LEAD SOIC WIDE PACKAGE  
CASE 751D–05  
The MC74VHCT240A is an inverting 3–state buffer, and has two  
active–low output enables. This device is designed to be used with  
3–state memory address drivers, etc.  
The VHCT inputs are compatible with TTL levels. This device can  
be used as a level converter for interfacing 3.3V to 5.0V, because it has  
full 5V CMOS level output swings.  
The VHCT240A input and output (when disabled) structures  
provide protection when voltages between 0V and 5.5V are applied,  
regardless of the supply voltage. These input and output structures  
help prevent device destruction caused by supply voltage –  
input/output voltage mismatch, battery backup, hot insertion, etc.  
DT SUFFIX  
20–LEAD TSSOP PACKAGE  
CASE 948E–02  
High Speed: t = 5.6ns (Typ) at V = 5V  
PD  
CC  
Low Power Dissipation: I = 4µA (Max) at T = 25°C  
CC  
A
TTL–Compatible Inputs: V = 0.8V; V = 2.0V  
Power Down Protection Provided on Inputs and Outputs  
Balanced Propagation Delays  
M SUFFIX  
20–LEAD SOIC EIAJ PACKAGE  
CASE 967–01  
IL  
IH  
ORDERING INFORMATION  
Designed for 4.5V to 5.5V Operating Range  
MC74VHCTXXXADW  
MC74VHCTXXXADT  
MC74VHCTXXXAM  
SOIC WIDE  
TSSOP  
SOIC EIAJ  
Low Noise: V  
= 1.1V (Max)  
OLP  
Pin and Function Compatible with Other Standard Logic Families  
Latchup Performance Exceeds 300mA  
ESD Performance: HBM > 2000V; Machine Model > 200V  
Chip Complexity: 110 FETs or 27.5 Equivalent Gates  
FUNCTION TABLE  
2
4
6
8
18  
16  
14  
12  
A1  
A2  
A3  
A4  
YA1  
YA2  
YA3  
YA4  
INPUTS  
OEA, OEB  
OUTPUTS  
YA, YB  
A, B  
L
L
H
L
H
X
H
L
Z
DATA  
INVERTING  
OUTPUTS  
OEA  
A1  
1
2
3
4
5
6
7
8
9
20  
V
CC  
INPUTS  
11  
13  
15  
17  
9
7
5
3
B1  
B2  
B3  
B4  
YB1  
YB2  
YB3  
YB4  
19 OEB  
18 YA1  
17 B4  
16 YA2  
15 B3  
14 YA3  
13 B2  
12 YA4  
11 B1  
YB4  
A2  
YB3  
A3  
YB2  
A4  
YB1  
1
GND 10  
OEA  
OEB  
OUTPUT  
19  
ENABLES  
Figure 1. Logic Diagram  
Figure 2. Pin Assignment  
Semiconductor Components Industries, LLC, 2001  
1
Publication Order Number:  
MC74VHCT240A/D  
March, 2001 – Rev. 3  

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