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MC74VHC1GT00DTR2 PDF预览

MC74VHC1GT00DTR2

更新时间: 2024-11-01 14:53:15
品牌 Logo 应用领域
安森美 - ONSEMI 输入元件光电二极管逻辑集成电路
页数 文件大小 规格书
6页 113K
描述
AHC/VHC SERIES, 2-INPUT NAND GATE, PDSO5, SC-59, SOT-23, TSOP-5

MC74VHC1GT00DTR2 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:TSOP
包装说明:TSOP,针数:5
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.59系列:AHC/VHC
JESD-30 代码:R-PDSO-G5JESD-609代码:e0
长度:3 mm逻辑集成电路类型:NAND GATE
功能数量:1输入次数:2
端子数量:5最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE峰值回流温度(摄氏度):NOT SPECIFIED
传播延迟(tpd):10.5 ns认证状态:Not Qualified
座面最大高度:1.1 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:TIN LEAD
端子形式:GULL WING端子节距:0.95 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:1.5 mmBase Number Matches:1

MC74VHC1GT00DTR2 数据手册

 浏览型号MC74VHC1GT00DTR2的Datasheet PDF文件第2页浏览型号MC74VHC1GT00DTR2的Datasheet PDF文件第3页浏览型号MC74VHC1GT00DTR2的Datasheet PDF文件第4页浏览型号MC74VHC1GT00DTR2的Datasheet PDF文件第5页浏览型号MC74VHC1GT00DTR2的Datasheet PDF文件第6页 
MC74VHC1GT00  
Single 2-Input NAND Gate/  
CMOS Logic Level Shifter  
LSTTLCompatible Inputs  
The MC74VHC1GT00 is a single gate 2input NAND fabricated  
with silicon gate CMOS technology.  
http://onsemi.com  
MARKING  
The internal circuit is composed of multiple stages, including a  
buffer output which provides high noise immunity and stable output.  
The device input is compatible with TTLtype input thresholds and  
the output has a full 5 V CMOS level output swing. The input  
protection circuitry on this device allows overvoltage tolerance on the  
input, allowing the device to be used as a logiclevel translator from  
3 V CMOS logic to 5 V CMOS Logic or from 1.8 V CMOS logic to  
3 V CMOS Logic while operating at the high voltage power supply.  
The MC74VHC1GT00 input structure provides protection when  
voltages up to 7 V are applied, regardless of the supply voltage. This  
allows the MC74VHC1GT00 to be used to interface 5 V circuits to  
3 V circuits. The output structures also provide protection  
DIAGRAMS  
5
5
1
VH M G  
SC88A / SC705 / SOT353  
DF SUFFIX  
G
CASE 419A  
1
5
5
VH M G  
G
1
when V = 0 V. These input and output structures help prevent  
CC  
1
TSOP5 / SOT235 / SC595  
DT SUFFIX  
device destruction caused by supply voltage input/output voltage  
mismatch, battery backup, hot insertion, etc.  
CASE 483  
Features  
VH = Device Code  
High Speed: t = 3.1 ns (Typ) at V = 5 V  
M
G
= Date Code*  
= PbFree Package  
PD  
CC  
Low Power Dissipation: I = 1 mA (Max) at T = 25°C  
CC  
A
(Note: Microdot may be in either location)  
*Date Code orientation and/or position may vary  
depending upon manufacturing location.  
TTLCompatible Inputs: V = 0.8 V; V = 2 V  
IL  
IH  
CMOSCompatible Outputs: V > 0.8 V ; V < 0.1 V @Load  
OH  
CC  
OL  
CC  
Power Down Protection Provided on Inputs and Outputs  
Balanced Propagation Delays  
Pin and Function Compatible with Other Standard Logic Families  
Chip Complexity: FETs = 64  
These Devices are PbFree and are RoHS Compliant  
PIN ASSIGNMENT  
1
2
3
4
5
IN B  
IN A  
GND  
OUT Y  
V
CC  
5
IN B  
IN A  
GND  
1
2
3
V
CC  
FUNCTION TABLE  
Inputs  
Output  
Y
A
B
4
OUT Y  
L
L
L
H
L
H
H
H
L
Figure 1. Pinout  
H
H
H
IN A  
IN B  
&
OUT Y  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
Figure 2. Logic Symbol  
dimensions section on page 4 of this data sheet.  
© Semiconductor Components Industries, LLC, 2011  
1
Publication Order Number:  
May, 2011 Rev. 12  
MC74VHC1GT00/D  

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