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MC74VHC1GT00DTT1 PDF预览

MC74VHC1GT00DTT1

更新时间: 2024-11-01 02:54:27
品牌 Logo 应用领域
安森美 - ONSEMI 转换器电平转换器栅极触发器逻辑集成电路光电二极管
页数 文件大小 规格书
6页 73K
描述
Single 2−Input NAND Gate/CMOS Logic Level Shifter LSTTL−Compatible Inputs

MC74VHC1GT00DTT1 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSOP包装说明:TSSOP, TSOP5/6,.11,37
针数:5Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.39
系列:AHC/VHCJESD-30 代码:R-PDSO-G5
JESD-609代码:e0长度:3 mm
逻辑集成电路类型:NAND GATE最大I(ol):0.008 A
湿度敏感等级:1功能数量:1
输入次数:2端子数量:5
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSOP5/6,.11,37封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TAPE AND REEL
峰值回流温度(摄氏度):240电源:3.3/5 V
Prop。Delay @ Nom-Sup:10.5 ns传播延迟(tpd):17.5 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:1.1 mm子类别:Gates
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.95 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:1.5 mm
Base Number Matches:1

MC74VHC1GT00DTT1 数据手册

 浏览型号MC74VHC1GT00DTT1的Datasheet PDF文件第2页浏览型号MC74VHC1GT00DTT1的Datasheet PDF文件第3页浏览型号MC74VHC1GT00DTT1的Datasheet PDF文件第4页浏览型号MC74VHC1GT00DTT1的Datasheet PDF文件第5页浏览型号MC74VHC1GT00DTT1的Datasheet PDF文件第6页 
MC74VHC1GT00  
Single 2−Input NAND Gate/  
CMOS Logic Level Shifter  
LSTTL−Compatible Inputs  
The MC74VHC1GT00 is a single gate 2−input NAND fabricated  
with silicon gate CMOS technology.  
http://onsemi.com  
MARKING  
The internal circuit is composed of multiple stages, including a  
buffer output which provides high noise immunity and stable output.  
The device input is compatible with TTL−type input thresholds and  
the output has a full 5 V CMOS level output swing. The input  
protection circuitry on this device allows overvoltage tolerance on the  
input, allowing the device to be used as a logic−level translator from  
3 V CMOS logic to 5 V CMOS Logic or from 1.8 V CMOS logic to  
3 V CMOS Logic while operating at the high voltage power supply.  
The MC74VHC1GT00 input structure provides protection when  
voltages up to 7 V are applied, regardless of the supply voltage. This  
allows the MC74VHC1GT00 to be used to interface 5 V circuits to  
3 V circuits. The output structures also provide protection  
DIAGRAMS  
5
5
1
VH M G  
SC−88A/SC70−5/SOT−353  
DF SUFFIX  
G
CASE 419A  
1
5
5
VH M G  
G
1
when V = 0 V. These input and output structures help prevent  
CC  
1
TSOP−5/SOT23−5/SC59−5  
DT SUFFIX  
device destruction caused by supply voltage − input/output voltage  
mismatch, battery backup, hot insertion, etc.  
CASE 483  
Features  
VH = Device Code  
High Speed: t = 3.1 ns (Typ) at V = 5 V  
M
G
= Date Code*  
= Pb−Free Package  
PD  
CC  
Low Power Dissipation: I = 1 mA (Max) at T = 25°C  
CC  
A
(Note: Microdot may be in either location)  
*Date Code orientation and/or position may vary  
depending upon manufacturing location.  
TTL−Compatible Inputs: V = 0.8 V; V = 2 V  
IL  
IH  
CMOS−Compatible Outputs: V > 0.8 V ; V < 0.1 V @Load  
OH  
CC  
OL  
CC  
Power Down Protection Provided on Inputs and Outputs  
Balanced Propagation Delays  
Pin and Function Compatible with Other Standard Logic Families  
Chip Complexity: FETs = 64  
Pb−Free Packages are Available  
PIN ASSIGNMENT  
1
2
3
4
5
IN B  
IN A  
GND  
OUT Y  
V
CC  
5
4
IN B  
IN A  
GND  
1
2
3
V
CC  
FUNCTION TABLE  
Inputs  
Output  
Y
A
B
OUT Y  
L
L
L
H
L
H
H
H
L
Figure 1. Pinout  
H
H
H
IN A  
IN B  
&
OUT Y  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 4 of this data sheet.  
Figure 2. Logic Symbol  
©
Semiconductor Components Industries, LLC, 2007  
1
Publication Order Number:  
February, 2007 − Rev. 11  
MC74VHC1GT00/D  

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