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MC74VHC1G125P5T5G PDF预览

MC74VHC1G125P5T5G

更新时间: 2024-11-05 11:10:47
品牌 Logo 应用领域
安森美 - ONSEMI 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
15页 478K
描述
单非逆变缓冲器,3 态

MC74VHC1G125P5T5G 技术参数

是否无铅: 不含铅生命周期:Active
包装说明:SOT-953, 5 PINReach Compliance Code:compliant
Factory Lead Time:43 weeks 1 day风险等级:5.61
控制类型:ENABLE LOW系列:AHC/VHC
JESD-30 代码:R-PDSO-F5长度:1 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.008 A位数:1
功能数量:1端口数量:2
端子数量:5最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:VSOF封装等效代码:FL5/6,.03,14
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, VERY THIN PROFILE
包装方法:TR峰值回流温度(摄氏度):NOT SPECIFIED
最大电源电流(ICC):0.04 mAProp。Delay @ Nom-Sup:10.5 ns
传播延迟(tpd):16 ns座面最大高度:0.4 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子形式:FLAT端子节距:0.35 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:0.8 mmBase Number Matches:1

MC74VHC1G125P5T5G 数据手册

 浏览型号MC74VHC1G125P5T5G的Datasheet PDF文件第2页浏览型号MC74VHC1G125P5T5G的Datasheet PDF文件第3页浏览型号MC74VHC1G125P5T5G的Datasheet PDF文件第4页浏览型号MC74VHC1G125P5T5G的Datasheet PDF文件第5页浏览型号MC74VHC1G125P5T5G的Datasheet PDF文件第6页浏览型号MC74VHC1G125P5T5G的Datasheet PDF文件第7页 
DATA SHEET  
www.onsemi.com  
MARKING  
DIAGRAMS  
Noninverting 3-State Buffer  
MC74VHC1G125,  
MC74VHC1GT125  
The MC74VHC1G125 / MC74VHC1GT125 is a single  
noninverting 3state buffer in tiny footprint packages. The  
MC74VHC1G125 has CMOSlevel input thresholds while the  
MC74VHC1GT125 has TTLlevel input thresholds.  
The internal circuit is composed of three stages, including a buffered  
3state output which provides high noise immunity and stable output.  
The input structures provide protection when voltages up to 5.5 V  
are applied, regardless of the supply voltage. This allows the device to  
be used to interface 5 V circuits to 3 V circuits. Some output structures  
SC88A  
DF SUFFIX  
CASE 419A  
XX MG  
G
SC74A  
DBV SUFFIX  
CASE 318BQ  
XXX MG  
G
SOT953  
P5 SUFFIX  
CASE 527AE  
X M  
1
also provide protection when V = 0 V and when the output voltage  
CC  
UDFN6  
1.45 x 1.0  
CASE 517AQ  
exceeds V . These input and output structures help prevent device  
CC  
XM  
X M  
X M  
destruction caused by supply voltage input/output voltage mismatch,  
battery backup, hot insertion, etc.  
1
1
UDFN6  
1.2 x 1.0  
CASE 517AA  
Features  
Designed for 2.0 V to 5.5 V V Operation  
CC  
3.5 ns t at 5 V (typ)  
PD  
Inputs/Outputs OverVoltage Tolerant up to 5.5 V  
UDFN6  
1.0 x 1.0  
CASE 517BX  
I  
Supports Partial Power Down Protection  
Source/Sink 8 mA at 3.0 V  
OFF  
1
Available in SC88A, SC74A, SOT953 and UDFN6 Packages  
Chip Complexity < 100 FETs  
XX  
M
G
= Specific Device Code  
= Date Code*  
= PbFree Package  
Q Suffix for Automotive and Other Applications Requiring Unique  
Site and Control Change Requirements; AECQ100 Qualified and  
PPAP Capable  
(Note: Microdot may be in either location)  
*Date Code orientation and/or position may  
vary depending upon manufacturing location.  
These Devices are PbFree, Halogen Free/BFR Free and are RoHS  
Compliant  
ORDERING INFORMATION  
OE  
A
EN  
Y
See detailed ordering, marking and shipping information in the  
package dimensions section on page 8 of this data sheet.  
Figure 1. Logic Symbol  
© Semiconductor Components Industries, LLC, 2012  
1
Publication Order Number:  
April, 2023 Rev. 22  
MC74VHC1G125/D  

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