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MC74VHC1G05DTT1 PDF预览

MC74VHC1G05DTT1

更新时间: 2024-01-21 19:30:57
品牌 Logo 应用领域
ETL 触发器逻辑集成电路光电二极管
页数 文件大小 规格书
4页 578K
描述
Inverter with Open Drain Output

MC74VHC1G05DTT1 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:TSOP
包装说明:SC-59, SOT-23, TSOP-5针数:5
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:5.54
系列:AHC/VHCJESD-30 代码:R-PDSO-G5
JESD-609代码:e0长度:3 mm
负载电容(CL):50 pF逻辑集成电路类型:INVERTER
最大I(ol):0.008 A湿度敏感等级:1
功能数量:1输入次数:1
端子数量:5最高工作温度:125 °C
最低工作温度:-55 °C输出特性:OPEN-DRAIN
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSOP5/6,.11,37封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):240
电源:2/5.5 VProp。Delay @ Nom-Sup:10 ns
传播延迟(tpd):14.5 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:1.1 mm
子类别:Gates最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.95 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:1.5 mmBase Number Matches:1

MC74VHC1G05DTT1 数据手册

 浏览型号MC74VHC1G05DTT1的Datasheet PDF文件第2页浏览型号MC74VHC1G05DTT1的Datasheet PDF文件第3页浏览型号MC74VHC1G05DTT1的Datasheet PDF文件第4页 
Inverter with Open Drain  
Output  
MC74VHC1G05  
The MC74VHC1G05 is an advanced high speed CMOS inverter with open drain output fabricated with silicon gate CMOS technology.  
It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation.  
The internal circuit is composed of three stages, including an open drain output which provides the capability to set output switching  
level. This allows the MC74VHC1G05 to be used to interface 5 V circuits to circuits of any voltage between V CC and 7 V using an external  
resistor and power supply.  
The MC74VHC1G05 input structure provides protection when voltages up to 7 V are applied, regardless of the supply voltage.  
• High Speed: t PD = 3.8 ns (Typ) at V CC = 5 V  
• Low Internal Power Dissipation: I CC = 2 mA (Max) at T A = 25°C  
• Power Down Protection Provided on Inputs  
• Pin and Function Compatible with Other Standard Logic Families  
• Chip Complexity: FET = 105; Equivalent Gate = 26  
MARKING DIAGRAMS  
5
4
1
2
VFd  
3
SC–88A / SOT–353/SC–70  
DF SUFFIX  
CASE 419A  
Pin 1  
d = Date Code  
5
Figure 1. Pinout (Top View)  
4
VFd  
1
2
3
Figure 2. Logic Symbol  
TSOP–5/SOT–23/SC–59  
DT SUFFIX  
CASE 483  
Pin 1  
d = Date Code  
FUNCTION TABLE  
Inputs  
Output  
PIN ASSIGNMENT  
A
L
Y
Z
L
1
2
3
4
5
NC  
IN A  
H
GND  
OUT Y  
V CC  
ORDERING INFORMATION  
See detailed ordering and shipping information in the  
package dimensions section on page 4 of this data sheet.  
VH5–1/4  

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