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MC74LCX652 PDF预览

MC74LCX652

更新时间: 2024-11-04 23:05:47
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
9页 181K
描述
LOW.VOLTAGE CMOS OCTAL TRANSCEIVER/ REGISTERED TRANSCEIVER WITH DUAL ENABLE

MC74LCX652 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MC74LCX652 is a high performance, non–inverting octal  
transceiver/registered transceiver operating from a 2.7 to 3.6V supply.  
High impedance TTL compatible inputs significantly reduce current  
loading to input drivers while TTL compatible outputs offer improved  
LOW–VOLTAGE CMOS  
OCTAL TRANSCEIVER/  
REGISTERED TRANSCEIVER  
WITH DUAL ENABLE  
switching noise performance. A V specification of 5.5V allows  
I
MC74LCX652 inputs to be safely driven from 5V devices. The  
MC74LCX652 is suitable for memory address driving and all TTL level  
bus oriented transceiver applications.  
Data on the A or B bus will be clocked into the registers as the  
appropriate clock pin goes from a LOW–to–HIGH logic level. Two Output  
Enable pins (OEBA, OEAB) are provided to control the transceiver  
outputs. In the transceiver mode, data present at the high impedance port  
may be stored in either the A or the B register or in both. The select  
controls (SBA, SAB) can multiplex stored and real–time (transparent  
mode) data. In the isolation mode (both outputs disabled), A data may be  
stored in the B register or B data may be stored in the A register. When in  
the real–time mode, it is possible to store data without using the internal  
registers by simultaneously enabling OEAB and OEBA. In this  
configuration, each output reinforces its input (data retention is not  
guaranteed in this mode).  
DW SUFFIX  
24–LEAD PLASTIC SOIC PACKAGE  
CASE 751E–04  
SD SUFFIX  
24–LEAD PLASTIC SSOP PACKAGE  
CASE 940D–03  
Designed for 2.7 to 3.6V V  
CC  
Operation  
5V Tolerant — Interface Capability With 5V TTL Logic  
Supports Live Insertion and Withdrawal  
I  
OFF  
Specification Guarantees High Impedance When V  
= 0V  
CC  
DT SUFFIX  
24–LEAD PLASTIC TSSOP PACKAGE  
CASE 948H–01  
LVTTL Compatible  
LVCMOS Compatible  
24mA Balanced Output Sink and Source Capability  
Near Zero Static Supply Current in All Three Logic States (10µA)  
Substantially Reduces System Power Requirements  
PIN NAMES  
Latchup Performance Exceeds 500mA  
Pins  
Function  
ESD Performance: Human Body Model >2000V; Machine Model >200V  
A0–A7  
B0–B7  
CAB, CBA  
SAB, SBA  
OEBA, OEAB  
Side A Inputs/Outputs  
Side B Inputs/Outputs  
Clock Pulse Inputs  
Select Control Inputs  
Output Enable Inputs  
V
CBA SBA OEBA B0  
B1  
19  
B2  
18  
B3  
17  
B4  
16  
B5  
15  
B6  
14  
B7  
13  
CC  
24  
23  
22  
21  
20  
1
2
3
4
5
6
7
9
11  
8
10  
A6  
12  
CAB SAB OEAB A0  
A1  
A2  
A3  
A4  
A5  
A7 GND  
Figure 1. 24–Lead Pinout (Top View)  
3/97  
Motorola, Inc. 1997  
REV 1  

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