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MC74LCX652DW

更新时间： 2024-11-05 23:05:47
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA /
页数 文件大小 规格书
9页 181K
描述
LOW-VOLTAGE CMOS OCTAL TRANSCEIVER/ REGISTERED TRANSCEIVER WITH DUAL ENABLE

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中文翻译

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MC74LCX652DW 技术参数

生命周期：Transferred零件包装代码：SOIC
包装说明：SOP, SOP24,.4针数：24
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.19其他特性：INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION
控制类型：INDEPENDENT CONTROL计数方向：BIDIRECTIONAL
系列：LVC/LCX/ZJESD-30 代码：R-PDSO-G24
JESD-609代码：e0长度：15.4 mm
负载电容（CL）：50 pF逻辑集成电路类型：REGISTERED BUS TRANSCEIVER
最大I（ol）：0.024 A位数：8
功能数量：1端口数量：2
端子数量：24最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP24,.4
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
电源：3.3 VProp。Delay @ Nom-Sup：7 ns
传播延迟（tpd）：9.5 ns认证状态：Not Qualified
座面最大高度：2.65 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
触发器类型：POSITIVE EDGE宽度：7.5 mm
Base Number Matches：1

MC74LCX652DW 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MC74LCX652 is a high performance, non–inverting octal  
transceiver/registered transceiver operating from a 2.7 to 3.6V supply.  
High impedance TTL compatible inputs significantly reduce current  
loading to input drivers while TTL compatible outputs offer improved  
LOW–VOLTAGE CMOS  
OCTAL TRANSCEIVER/  
REGISTERED TRANSCEIVER  
WITH DUAL ENABLE  
switching noise performance. A V specification of 5.5V allows  
I
MC74LCX652 inputs to be safely driven from 5V devices. The  
MC74LCX652 is suitable for memory address driving and all TTL level  
bus oriented transceiver applications.  
Data on the A or B bus will be clocked into the registers as the  
appropriate clock pin goes from a LOW–to–HIGH logic level. Two Output  
Enable pins (OEBA, OEAB) are provided to control the transceiver  
outputs. In the transceiver mode, data present at the high impedance port  
may be stored in either the A or the B register or in both. The select  
controls (SBA, SAB) can multiplex stored and real–time (transparent  
mode) data. In the isolation mode (both outputs disabled), A data may be  
stored in the B register or B data may be stored in the A register. When in  
the real–time mode, it is possible to store data without using the internal  
registers by simultaneously enabling OEAB and OEBA. In this  
configuration, each output reinforces its input (data retention is not  
guaranteed in this mode).  
DW SUFFIX  
24–LEAD PLASTIC SOIC PACKAGE  
CASE 751E–04  
SD SUFFIX  
24–LEAD PLASTIC SSOP PACKAGE  
CASE 940D–03  
• Designed for 2.7 to 3.6V V  
CC  
Operation  
• 5V Tolerant — Interface Capability With 5V TTL Logic  
• Supports Live Insertion and Withdrawal  
• I  
OFF  
Specification Guarantees High Impedance When V  
= 0V  
CC  
DT SUFFIX  
24–LEAD PLASTIC TSSOP PACKAGE  
CASE 948H–01  
• LVTTL Compatible  
• LVCMOS Compatible  
• 24mA Balanced Output Sink and Source Capability  
• Near Zero Static Supply Current in All Three Logic States (10µA)  
Substantially Reduces System Power Requirements  
PIN NAMES  
• Latchup Performance Exceeds 500mA  
Pins  
Function  
• ESD Performance: Human Body Model >2000V; Machine Model >200V  
A0–A7  
B0–B7  
CAB, CBA  
SAB, SBA  
OEBA, OEAB  
Side A Inputs/Outputs  
Side B Inputs/Outputs  
Clock Pulse Inputs  
Select Control Inputs  
Output Enable Inputs  
V
CBA SBA OEBA B0  
B1  
19  
B2  
18  
B3  
17  
B4  
16  
B5  
15  
B6  
14  
B7  
13  
CC  
24  
23  
22  
21  
20  
1
2
3
4
5
6
7
9
11  
8
10  
A6  
12  
CAB SAB OEAB A0  
A1  
A2  
A3  
A4  
A5  
A7 GND  
Figure 1. 24–Lead Pinout (Top View)  
3/97  
Motorola, Inc. 1997  
REV 1  
1234567...9

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