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MC74HC640N PDF预览

MC74HC640N

更新时间: 2024-11-11 13:11:19
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 总线收发器
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6页 205K
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MC74HC640N 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
High–Performance Silicon–Gate CMOS  
J SUFFIX  
CERAMIC PACKAGE  
CASE 732–03  
20  
20  
The MC54/74HC640A is identical in pinout to the LS640. The device  
inputs are compatible with standard CMOS outputs; with pullup resistors,  
they are compatible with LSTTL outputs.  
The HC640A is a 3–state transceiver that is used for 2–way asynchronous  
communication between data buses. The device has an active–low Output  
Enable pin, which is used to place the I/O ports into high–impedance states.  
The Direction control determines whether data flows from A to B or from B  
to A.  
1
N SUFFIX  
PLASTIC PACKAGE  
CASE 738–03  
1
Output Drive Capability: 15 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2 to 6 V  
DW SUFFIX  
SOIC PACKAGE  
CASE 751D–04  
20  
1
Low Input Current: 1 µA  
ORDERING INFORMATION  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
MC54HCXXXAJ  
MC74HCXXXAN  
MC74HCXXXADW  
Ceramic  
Plastic  
SOIC  
Chip Complexity: 276 FETs or 69 Equivalent Gates  
LOGIC DIAGRAM  
PIN ASSIGNMENT  
2
3
4
5
6
7
8
9
18  
17  
16  
15  
14  
13  
12  
11  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
B8  
DIRECTION  
1
20  
V
CC  
OUTPUT  
ENABLE  
A1  
A2  
2
3
19  
18  
B1  
A
DATA  
PORT  
B
DATA  
PORT  
A3  
4
17  
B2  
A4  
A5  
5
16  
15  
14  
13  
12  
11  
B3  
B4  
B5  
B6  
B7  
B8  
6
A6  
7
A7  
8
1
DIRECTION  
A8  
9
19  
OUTPUT ENABLE  
GND  
10  
PIN 10 = GND  
PIN 20 = V  
CC  
FUNCTION TABLE  
Control Inputs  
Output  
Enable  
Operation  
Direction  
L
L
Data Transmitted from Bus B  
to Bus A (Inverted)  
L
H
X
Data Transmitted from Bus A  
to Bus B (Inverted)  
H
Buses Isolated  
(High–Impedance State)  
X = don’t care  
10/95  
REV 6  
Motorola, Inc. 1995  

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