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MC74HC646 PDF预览

MC74HC646

更新时间: 2024-09-22 21:55:07
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 总线收发器触发器
页数 文件大小 规格书
14页 331K
描述
Octal 3-State Bus Transceivers and D Flip-Flops

MC74HC646 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
High–Performance Silicon–Gate CMOS  
J SUFFIX  
CERAMIC PACKAGE  
CASE 758–02  
The MC54/74HC646 is identical in pinout to the LS646. The device inputs  
are compatible with standard CMOS outputs; with pullup resistors, they are  
compatible with LSTTL outputs.  
24  
1
These devices are bus transceivers with D flip–flops. Depending on the  
status of the Data–Source Selection pins, data may be routed to the outputs  
either from the flip–flops or transmitted real–time from the inputs (see  
Function Table and Application Information).  
The Output Enable and the Direction pins control the transceiver’s  
function. Bus A and Bus B cannot be routed as outputs to each other  
simultaneously, but can be routed as inputs to the A and B flip–flops. Also,  
the A and B flip–flops can be routed as outputs to Bus A and Bus B.  
Additionally, when either or both of the ports are in the high–impedance  
state, these I/O pins may be used as inputs to the D flip–flops for data  
storage.  
N SUFFIX  
PLASTIC PACKAGE  
CASE 724–03  
24  
1
DW SUFFIX  
SOIC PACKAGE  
CASE 751E–04  
24  
1
The user should note that because the clocks are not gated with the  
Direction and Output Enable pins, data at the A and B ports may be clocked  
into the storage flip–flops at any time.  
ORDERING INFORMATION  
MC54HCXXXJ  
MC74HCXXXN  
MC74HCXXXDW  
Ceramic  
Plastic  
SOIC  
Output Drive Capability: 15 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2 to 6 V  
Low Input Current: 1 µA  
PIN ASSIGNMENT  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
A–TO–B  
1
2
3
4
5
6
24  
23  
22  
21  
20  
19  
V
CC  
CLOCK  
B–TO–A  
CLOCK  
A–TO–B  
SOURCE  
DIRECTION  
Chip Complexity: 780 FETs or 195 Equivalent Gates  
B–TO–A  
SOURCE  
OUTPUT ENABLE  
A0  
A1  
A2  
B0  
B1  
LOGIC DIAGRAM  
4
5
6
7
20  
19  
18  
17  
A3  
A4  
7
18  
17  
16  
15  
14  
13  
B2  
B3  
B4  
B5  
B6  
B7  
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
B0  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
8
A5  
9
A
DATA  
PORT  
B
DATA  
PORT  
8
9
10  
16  
15  
14  
A6  
10  
11  
12  
A7  
GND  
11  
13  
21  
OUTPUT ENABLE  
3
1
DIRECTION  
FLIP–FLOP  
CLOCKS  
A–TO–B CLOCK  
23  
2
B–TO–A CLOCK  
A–TO–B SOURCE  
B–TO–A SOURCE  
DATA SOURCE  
SELECTION  
INPUTS  
22  
PIN 24 = V  
PIN 12 = GND  
CC  
10/95  
Motorola, Inc. 1995  
REV 6  

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