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MC74HC597 PDF预览

MC74HC597

更新时间: 2024-11-10 22:41:03
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 移位寄存器
页数 文件大小 规格书
9页 249K
描述
8-Bit Serial or Parallel-Input/Serial-Output Shift Register with Input Latch

MC74HC597 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
J SUFFIX  
CERAMIC PACKAGE  
CASE 620–10  
High–Performance Silicon–Gate CMOS  
16  
1
The MC54/74HC597 is identical in pinout to the LS597. The device inputs  
are compatible with standard CMOS outputs; with pullup resistors, they are  
compatible with LSTTL outputs.  
N SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
This device consists of an 8–bit input latch which feeds parallel data to an  
8–bit shift register. Data can also be loaded serially (see Function Table).  
The HC597 is similar in function to the HC589, which is a 3–state device.  
16  
1
Output Drive Capability: 10 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2 to 6 V  
D SUFFIX  
SOIC PACKAGE  
CASE 751B–05  
16  
Low Input Current: 1 µA  
1
High Noise Immunity Characteristic of CMOS Devices  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
ORDERING INFORMATION  
Chip Complexity: 516 FETs or 129 Equivalent Gates  
MC54HCXXXJ  
MC74HCXXXN  
MC74HCXXXD  
Ceramic  
Plastic  
SOIC  
LOGIC DIAGRAM  
SERIAL  
DATA  
INPUT  
14  
PIN ASSIGNMENT  
S
A
B
C
1
2
16  
15  
V
A
S
CC  
15  
1
A
B
D
E
3
4
5
6
7
8
14  
13  
12  
11  
10  
9
A
2
3
4
5
SERIAL SHIFT/  
PARALLEL LOAD  
C
PARALLEL  
DATA  
INPUTS  
D
E
F
F
LATCH CLOCK  
SHIFT CLOCK  
RESET  
INPUT  
LATCH  
SHIFT  
REGISTER  
G
H
6
7
G
H
SERIAL  
DATA  
OUTPUT  
GND  
Q
H
9
Q
H
12  
LATCH CLOCK  
11  
SHIFT CLOCK  
PIN 16 = V  
PIN 8 = GND  
CC  
SERIAL SHIFT/ 13  
PARALLEL LOAD  
10  
RESET  
10/95  
Motorola, Inc. 1995  
REV 6  

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