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MC74HC597ADR2 PDF预览

MC74HC597ADR2

更新时间: 2024-11-09 15:41:03
品牌 Logo 应用领域
安森美 - ONSEMI 光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
11页 291K
描述
HC/UH SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16, PLASTIC, SOIC-16

MC74HC597ADR2 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:PLASTIC, SOIC-16
针数:16Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.18
计数方向:RIGHT系列:HC/UH
JESD-30 代码:R-PDSO-G16JESD-609代码:e0
长度:9.9 mm逻辑集成电路类型:PARALLEL IN SERIAL OUT
位数:8功能数量:1
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED传播延迟(tpd):275 ns
认证状态:Not Qualified座面最大高度:1.75 mm
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):3 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:3.9 mm最小 fmax:40 MHz
Base Number Matches:1

MC74HC597ADR2 数据手册

 浏览型号MC74HC597ADR2的Datasheet PDF文件第2页浏览型号MC74HC597ADR2的Datasheet PDF文件第3页浏览型号MC74HC597ADR2的Datasheet PDF文件第4页浏览型号MC74HC597ADR2的Datasheet PDF文件第5页浏览型号MC74HC597ADR2的Datasheet PDF文件第6页浏览型号MC74HC597ADR2的Datasheet PDF文件第7页 
SEMICONDUCTOR TECHNICAL DATA  
J SUFFIX  
CERAMIC PACKAGE  
CASE 620–10  
16  
1
High–Performance Silicon–Gate CMOS  
The MC54/74HC597A is identical in pinout to the LS597. The device  
inputs are compatible with standard CMOS outputs; with pullup resistors,  
they are compatible with LSTTL outputs.  
This device consists of an 8–bit input latch which feeds parallel data to an  
8–bit shift register. Data can also be loaded serially (see Function Table).  
The HC597A is similar in function to the HC589A, which is a 3–state  
device.  
N SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
16  
1
D SUFFIX  
Output Drive Capability: 10 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2 to 6 V  
16  
SOIC PACKAGE  
CASE 751B–05  
1
Low Input Current: 1 µA  
DT SUFFIX  
TSSOP PACKAGE  
CASE 948F–01  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
16  
1
Chip Complexity: 516 FETs or 129 Equivalent Gates  
ORDERING INFORMATION  
MC54HCXXXAJ  
Ceramic  
Plastic  
SOIC  
MC74HCXXXAN  
MC74HCXXXAD  
MC74HCXXXADT  
LOGIC DIAGRAM  
SERIAL  
14  
TSSOP  
DATA  
INPUT  
S
A
PIN ASSIGNMENT  
15  
1
A
B
B
C
1
2
16  
15  
V
A
S
CC  
2
3
4
5
C
PARALLEL  
DATA  
INPUTS  
D
E
F
D
E
3
4
5
6
7
8
14  
13  
12  
11  
10  
9
A
INPUT  
LATCH  
SHIFT  
REGISTER  
SERIAL SHIFT/  
PARALLEL LOAD  
F
LATCH CLOCK  
SHIFT CLOCK  
RESET  
6
7
G
H
SERIAL  
DATA  
OUTPUT  
G
9
Q
H
H
12  
LATCH CLOCK  
GND  
Q
H
11  
SHIFT CLOCK  
PIN 16 = V  
PIN 8 = GND  
CC  
SERIAL SHIFT/ 13  
PARALLEL LOAD  
10  
RESET  
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.  
10/95  
REV 0  
Motorola, Inc. 1995  

MC74HC597ADR2 替代型号

型号 品牌 替代类型 描述 数据表
74HC597D-T NXP

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