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MC74HC4538NDS

更新时间： 2024-11-04 13:11:19
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 振荡器
页数 文件大小 规格书
13页 371K
描述
Monostable Multivibrator, CMOS, PDIP16

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中文翻译

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MC74HC4538NDS 技术参数

是否Rohs认证：不符合生命周期：Obsolete
Reach Compliance Code：unknown风险等级：5.85
Is Samacsys：NJESD-30 代码：R-PDIP-T16
JESD-609代码：e0逻辑集成电路类型：MONOSTABLE MULTIVIBRATOR
端子数量：16最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装等效代码：DIP16,.3
封装形状：RECTANGULAR封装形式：IN-LINE
电源：2/6 V子类别：Prescaler/Multivibrators
表面贴装：NO技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUALBase Number Matches：1

MC74HC4538NDS 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
J SUFFIX  
CERAMIC PACKAGE  
CASE 620–10  
16  
16  
The MC54/74HC4538A is identical in pinout to the MC14538B. The device  
inputs are compatible with standard CMOS outputs; with pullup resistors,  
they are compatible with LSTTL outputs.  
This dual monostable multivibrator may be triggered by either the positive  
or the negative edge of an input pulse, and produces a precision output  
pulse over a wide range of pulse widths. Because the device has conditioned  
trigger inputs, there are no trigger–input rise and fall time restrictions. The  
1
N SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
1
output pulse width is determined by the external timing components, R and  
x
C . The device has a reset function which forces the Q output low and the Q  
output high, regardless of the state of the output pulse circuitry.  
x
D SUFFIX  
SOIC PACKAGE  
CASE 751B–05  
16  
•
•
•
Unlimited Rise and Fall Times Allowed on the Trigger Inputs  
Output Pulse is Independent of the Trigger Pulse Width  
± 10% Guaranteed Pulse Width Variation from Part to Part (Using the  
Same Test Jig)  
1
ORDERING INFORMATION  
MC54HCXXXXAJ  
MC74HCXXXXAN  
MC74HCXXXXAD  
Ceramic  
Plastic  
SOIC  
•
•
•
•
•
•
Output Drive Capability: 10 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS and TTL  
Operating Voltage Range: 3.0 to 6.0 V  
Low Input Current: 1.0 µA  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
PIN ASSIGNMENT  
GND  
1/R  
1
2
16  
15  
V
CC  
GND  
•
Chip Complexity: 145 FETs or 36 Equivalent Gates  
C
1
X
X
RESET 1  
A1  
3
4
5
6
7
8
14  
13  
12  
11  
10  
9
C 2/R 2  
X X  
RESET 2  
A2  
LOGIC DIAGRAM  
B1  
C
1
R 1  
X
X
Q1  
B2  
V
CC  
Q1  
Q2  
1
2
GND  
Q2  
6
7
4
5
Q1  
Q1  
A1  
B1  
TRIGGER  
INPUTS  
C
2
R 2  
X
X
V
CC  
FUNCTION TABLE  
3
RESET 1  
Inputs  
Outputs  
15  
14  
Reset  
A
B
Q
Q
10  
12  
11  
Q2  
Q2  
A2  
B2  
H
H
H
TRIGGER  
INPUTS  
L
9
H
H
X
H
L
X
Not Triggered  
Not Triggered  
13  
RESET 2  
H
H
L,H,  
L
H
L,H,  
Not Triggered  
Not Triggered  
PIN 16 = V  
CC  
PIN 8 = GND  
AND C ARE EXTERNAL COMPONENTS  
PIN 1 AND PIN 15 MUST BE HARD WIRED TO GND  
L
X
X
X
X
L
H
R
X
X
Not Triggered  
10/95  
Motorola, Inc. 1995  
REV 6  
1234567...13

中文翻译

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