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MC74HC237ND

更新时间： 2024-11-23 13:11:19
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 解码器解复用器
页数 文件大小 规格书
6页 209K
描述
Decoder/Driver, HC/UH Series, True Output, CMOS, PDIP16, 648-06

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中文翻译

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MC74HC237ND 数据手册

 浏览型号MC74HC237ND的Datasheet PDF文件第2页浏览型号MC74HC237ND的Datasheet PDF文件第3页浏览型号MC74HC237ND的Datasheet PDF文件第4页浏览型号MC74HC237ND的Datasheet PDF文件第5页浏览型号MC74HC237ND的Datasheet PDF文件第6页 
SEMICONDUCTOR TECHNICAL DATA  
High–Performance Silicon–Gate CMOS  
N SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
16  
The MC74HC237 is identical in pinout to the LS137, but has noninverting  
outputs. The device inputs are compatible with standard CMOS outputs; with  
pullup resistors, they are compatible with LSTTL outputs.  
1
The HC237 decodes a three–bit Address to one–of–eight active–high  
outputs. The device has a transparent latch for storage of the Address. Two  
Chip Selects, one active–low and one active–high, are provided to facilitate  
the demultiplexing, cascading, and chip–selecting functions.  
D SUFFIX  
SOIC PACKAGE  
CASE 751B–05  
16  
1
The demultiplexing function is accomplished by using the Address inputs  
to select the desired device output, and then by using one of the Chip  
Selects as a data input while holding the other one active.  
ORDERING INFORMATION  
MC74HCXXXN  
MC74HCXXXD  
Plastic  
SOIC  
The HC237 is the noninverting version of the HC137.  
•
•
•
•
•
•
Output Drive Capability: 10 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2 to 6 V  
PIN ASSIGNMENT  
Low Input Current: 1 µA  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance with the Requirements Defined by JEDEC Standard  
No 7A  
A0  
A1  
A2  
1
2
16  
15  
V
CC  
Y0  
Y1  
Y2  
Y3  
Y4  
Y5  
Y6  
3
4
14  
13  
•
Chip Complexity: 156 FETs or 39 Equivalent Gates  
LATCH ENABLE  
LOGIC DIAGRAM  
5
6
12  
11  
CS2  
CS1  
1
2
3
15  
14  
13  
12  
11  
10  
9
7
8
10  
9
Y7  
A0  
A1  
A2  
Y0  
Y1  
Y2  
Y3  
Y4  
Y5  
Y6  
Y7  
TRANSPARENT  
LATCH  
ADDRESS  
INPUTS  
GND  
ACTIVE–  
HIGH  
OUTPUTS  
1–OF–8  
DECODER  
LATCH  
ENABLE  
4
7
FUNCTION TABLE  
Inputs  
Outputs  
LE CS1 CS2 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7  
6
5
CHIP-  
SELECT  
INPUTS  
PIN 16 = V  
PIN 8 = GND  
CC  
CS1  
CS2  
X
X
X
L
H
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
H
L
L
L
L
H
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
H
L
L
L
H
L
L
L
L
H
L
H
H
H
L
X
X
X
*
* = Depends upon the Address previously applied while LE was  
at a low level.  
10/95  
Motorola, Inc. 1995  
REV 6  
123456

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