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MC74HC161ADTR2G PDF预览

MC74HC161ADTR2G

更新时间: 2024-11-01 13:11:19
品牌 Logo 应用领域
安森美 - ONSEMI 计数器触发器逻辑集成电路光电二极管
页数 文件大小 规格书
16页 147K
描述
Presettable Counter, TSSOP-16, 2500-REEL

MC74HC161ADTR2G 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP, TSSOP16,.25针数:16
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:5.14计数方向:UP
系列:HC/UHJESD-30 代码:R-PDSO-G16
JESD-609代码:e4长度:5 mm
负载电容(CL):50 pF负载/预设输入:YES
逻辑集成电路类型:BINARY COUNTER最大频率@ Nom-Sup:20000000 Hz
最大I(ol):0.004 A工作模式:SYNCHRONOUS
湿度敏感等级:1位数:4
功能数量:1端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:2/6 V
传播延迟(tpd):220 ns认证状态:Not Qualified
座面最大高度:1.2 mm子类别:Counters
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):3 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40触发器类型:POSITIVE EDGE
宽度:4.4 mmBase Number Matches:1

MC74HC161ADTR2G 数据手册

 浏览型号MC74HC161ADTR2G的Datasheet PDF文件第2页浏览型号MC74HC161ADTR2G的Datasheet PDF文件第3页浏览型号MC74HC161ADTR2G的Datasheet PDF文件第4页浏览型号MC74HC161ADTR2G的Datasheet PDF文件第5页浏览型号MC74HC161ADTR2G的Datasheet PDF文件第6页浏览型号MC74HC161ADTR2G的Datasheet PDF文件第7页 
MC74HC161A,  
MC74HC163A  
Presettable Counters  
High–Performance Silicon–Gate CMOS  
The MC74HC161A and HC163A are identical in pinout to the  
LS161 and LS163. The device inputs are compatible with standard  
CMOS outputs; with pull–up resistors, they are compatible with  
LSTTL outputs.  
The HC161A and HC163A are programmable 4–bit binary counters  
with asynchronous and synchronous reset, respectively.  
http://onsemi.com  
MARKING  
DIAGRAMS  
16  
Output Drive Capability: 10 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2.0 to 6.0 V  
16  
MC74HC16xAN  
AWLYYWW  
1
PDIP–16  
N SUFFIX  
CASE 648  
1
Low Input Current: 1.0 mA  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
16  
1
16  
Chip Complexity: 192 FETs or 48 Equivalent Gates  
HC16xA  
AWLYWW  
1
SO–16  
D SUFFIX  
RESET  
CLOCK  
1
2
16  
15  
V
CC  
CASE 751B  
RIPPLE  
CARRY OUT  
Q0  
3
4
14  
13  
P0  
P1  
P2  
P3  
16  
16  
Q1  
HC  
16xA  
ALYW  
1
5
6
7
8
12  
11  
10  
9
Q2  
TSSOP–16  
DT SUFFIX  
CASE 948F  
Q3  
1
ENABLE T  
LOAD  
ENABLE P  
GND  
x
A
= 1 or 3  
= Assembly Location  
Figure 1. Pin Assignment  
FUNCTION TABLE  
L, WL = Wafer Lot  
Y, YY = Year  
W, WW = Work Week  
ORDERING INFORMATION  
Inputs  
Output  
Q
Device  
Package  
Shipping  
Clock Reset* Load Enable P Enable T  
MC74HC161AN  
MC74HC161AD  
PDIP–16  
SOIC–16  
SOIC–16  
TSSOP–16  
2000/Box  
48/Rail  
L
X
L
H
H
H
X
X
H
L
X
X
H
X
L
Reset  
Load Preset Data  
Count  
H
H
H
H
MC74HC161ADR2  
MC74HC161ADT  
MC74HC161ADTR2  
2500/Reel  
96/Rail  
No Count  
No Count  
X
TSSOP–16 2500/Reel  
*HC163A only. HC161A is an Asynchronous Reset Device  
H = high level, L = low level, X = don’t care  
MC74HC163AN  
MC74HC163AD  
PDIP–16  
SOIC–16  
SOIC–16  
TSSOP–16  
2000/Box  
48/Rail  
MC74HC163ADR2  
MC74HC163ADT  
MC74HC163ADTR2  
2500/Reel  
96/Rail  
TSSOP–16 2500/Reel  
Semiconductor Components Industries, LLC, 2001  
1
Publication Order Number:  
June, 2001 – Rev. 9  
MC74HC161A/D  

MC74HC161ADTR2G 替代型号

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