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MC74HC125AFELG PDF预览

MC74HC125AFELG

更新时间: 2024-11-21 21:05:07
品牌 Logo 应用领域
安森美 - ONSEMI 驱动光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
7页 113K
描述
HC/UH SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, PDSO14, LEAD FREE, EIAJ, SO-14

MC74HC125AFELG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP, SOP14,.3针数:14
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:6.75控制类型:ENABLE LOW
系列:HC/UHJESD-30 代码:R-PDSO-G14
JESD-609代码:e4长度:10.2 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.006 A湿度敏感等级:3
位数:1功能数量:4
端口数量:2端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP14,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:2/6 V
Prop。Delay @ Nom-Sup:27 ns传播延迟(tpd):135 ns
认证状态:Not Qualified座面最大高度:2.05 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):3 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:5.275 mmBase Number Matches:1

MC74HC125AFELG 数据手册

 浏览型号MC74HC125AFELG的Datasheet PDF文件第2页浏览型号MC74HC125AFELG的Datasheet PDF文件第3页浏览型号MC74HC125AFELG的Datasheet PDF文件第4页浏览型号MC74HC125AFELG的Datasheet PDF文件第5页浏览型号MC74HC125AFELG的Datasheet PDF文件第6页浏览型号MC74HC125AFELG的Datasheet PDF文件第7页 
MC74HC125A,  
MC74HC126A  
Quad 3-State Noninverting  
Buffers  
High−Performance Silicon−Gate CMOS  
http://onsemi.com  
The MC74HC125A and MC74HC126A are identical in pinout to  
the LS125 and LS126. The device inputs are compatible with standard  
CMOS outputs; with pullup resistors, they are compatible with  
LSTTL outputs.  
The HC125A and HC126A noninverting buffers are designed to be  
used with 3−state memory address drivers, clock drivers, and other  
bus−oriented systems. The devices have four separate output enables  
that are active−low (HC125A) or active−high (HC126A).  
SOIC−14 NB  
D SUFFIX  
CASE 751A  
TSSOP−14  
DT SUFFIX  
CASE 948G  
PIN ASSIGNMENT  
Features  
OE1  
A1  
1
2
14  
13 OE4  
12  
V
CC  
Output Drive Capability: 15 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2.0 to 6.0 V  
Y1  
3
4
A4  
OE2  
11 Y4  
Low Input Current: 1.0 mA  
A2  
Y2  
5
6
10 OE3  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance with the JEDEC Standard No. 7 A Requirements  
Chip Complexity: 72 FETs or 18 Equivalent Gates  
9
8
A3  
Y3  
GND  
7
NLV Prefix for Automotive and Other Applications Requiring  
Unique Site and Control Change Requirements; AEC−Q100  
Qualified and PPAP Capable  
MARKING DIAGRAMS  
14  
14  
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS  
HC  
12xA  
ALYWG  
G
HC12xAG  
AWLYWW  
Compliant  
LOGIC DIAGRAM  
1
1
HC125A  
HC126A  
SOIC−14 NB  
TSSOP−14  
Active−Low Output Enables  
Active−High Output Enables  
x
= 5, 6  
A
L, WL  
Y, YY  
= Assembly Location  
= Wafer Lot  
= Year  
2
3
2
3
A1  
A1  
Y1  
Y2  
Y3  
Y1  
Y2  
Y3  
1
5
1
5
W, WW = Work Week  
OE1  
A2  
OE1  
A2  
G or G  
= Pb−Free Package  
6
6
(Note: Microdot may be in either location)  
4
9
4
9
OE2  
A3  
OE2  
A3  
FUNCTION TABLE  
HC125A  
HC126A  
8
8
Inputs Output  
Inputs Output  
A
OE  
Y
A
OE  
Y
10  
12  
10  
12  
OE3  
A4  
OE3  
A4  
H
L
X
L
L
H
H
L
Z
H
L
X
H
H
L
H
L
Z
11  
11  
Y4  
Y4  
13  
13  
OE4  
OE4  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 5 of this data sheet.  
PIN 14 = V  
CC  
PIN 7 = GND  
© Semiconductor Components Industries, LLC, 2014  
1
Publication Order Number:  
August, 2014 − Rev. 15  
MC74HC125A/D  

MC74HC125AFELG 替代型号

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