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MC74HC126ADTR2 PDF预览

MC74HC126ADTR2

更新时间: 2024-11-18 21:53:19
品牌 Logo 应用领域
安森美 - ONSEMI 逻辑集成电路光电二极管驱动
页数 文件大小 规格书
8页 174K
描述
Quad 3-State Noninverting Buffers

MC74HC126ADTR2 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:LEAD FREE, TSSOP-14
针数:14Reach Compliance Code:unknown
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:5.1Is Samacsys:N
控制类型:ENABLE HIGH系列:HC/UH
JESD-30 代码:R-PDSO-G14JESD-609代码:e4
长度:5 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.006 A
湿度敏感等级:1位数:1
功能数量:4端口数量:2
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:2/6 VProp。Delay @ Nom-Sup:27 ns
传播延迟(tpd):135 ns认证状态:Not Qualified
座面最大高度:1.2 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):3 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40宽度:4.4 mm
Base Number Matches:1

MC74HC126ADTR2 数据手册

 浏览型号MC74HC126ADTR2的Datasheet PDF文件第2页浏览型号MC74HC126ADTR2的Datasheet PDF文件第3页浏览型号MC74HC126ADTR2的Datasheet PDF文件第4页浏览型号MC74HC126ADTR2的Datasheet PDF文件第5页浏览型号MC74HC126ADTR2的Datasheet PDF文件第6页浏览型号MC74HC126ADTR2的Datasheet PDF文件第7页 
High–Performance Silicon–Gate CMOS  
http://onsemi.com  
The MC74HC125A and MC74HC126A are identical in pinout to  
the LS125 and LS126. The device inputs are compatible with standard  
CMOS outputs; with pullup resistors, they are compatible with  
LSTTL outputs.  
MARKING  
DIAGRAMS  
14  
The HC125A and HC126A noninverting buffers are designed to be  
used with 3–state memory address drivers, clock drivers, and other  
bus–oriented systems. The devices have four separate output enables  
that are active–low (HC125A) or active–high (HC126A).  
PDIP–14  
N SUFFIX  
CASE 646  
MC74HC12xAN  
AWLYYWW  
1
14  
Output Drive Capability: 15 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2.0 to 6.0 V  
Low Input Current: 1.0 µA  
SOIC–14  
D SUFFIX  
CASE 751A  
HC12xA  
AWLYWW  
1
14  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
HC  
12xA  
ALYW  
TSSOP–14  
DT SUFFIX  
CASE 948G  
Chip Complexity: 72 FETs or 18 Equivalent Gates  
1
LOGIC DIAGRAM  
A
= Assembly Location  
HC125A  
HC126A  
WL or L = Wafer Lot  
YY or Y = Year  
Active–Low Output Enables  
Active–High Output Enables  
WW or W = Work Week  
2
3
6
2
3
A1  
A1  
Y1  
Y2  
Y3  
Y1  
Y2  
Y3  
PIN ASSIGNMENT  
1
5
1
5
OE1  
A2  
OE1  
A2  
OE1  
A1  
1
2
14  
13 OE4  
12  
V
CC  
6
Y1  
3
4
A4  
4
9
4
9
OE2  
A3  
OE2  
A3  
OE2  
11 Y4  
8
8
A2  
Y2  
5
6
7
10 OE3  
9
8
A3  
Y3  
10  
12  
10  
12  
OE3  
A4  
OE3  
A4  
GND  
11  
11  
Y4  
Y4  
13  
13  
OE4  
OE4  
PIN 14 = V  
CC  
PIN 7 = GND  
ORDERING INFORMATION  
FUNCTION TABLE  
Device  
Package  
PDIP–14  
Shipping  
HC125A  
HC126A  
MC74HC12xAN  
2000 / Box  
55 / Rail  
Inputs Output  
Inputs Output  
MC74HC12xAD  
SOIC–14  
SOIC–14  
TSSOP–14  
TSSOP–14  
A
OE  
Y
A
OE  
Y
MC74HC12xADR2  
MC74HC12xADT  
MC74HC12xADTR2  
2500 / Reel  
96 / Rail  
H
L
X
L
L
H
H
L
Z
H
L
X
H
H
L
H
L
Z
2500 / Reel  
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
March, 2000 – Rev. 9  
MC74HC125A/D  

MC74HC126ADTR2 替代型号

型号 品牌 替代类型 描述 数据表
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