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MC74F112D PDF预览

MC74F112D

更新时间: 2024-11-11 22:54:55
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 触发器
页数 文件大小 规格书
3页 71K
描述
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

MC74F112D 数据手册

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MC74F112  
DUAL JK NEGATIVE  
EDGE-TRIGGERED FLIP-FLOP  
The MC74F112 contains two independent, high-speed JK flip-flops with Di-  
rect Set and Clear inputs. Synchronous state changes are initiated by the fal-  
ling edge of the clock. Triggering occurs at a voltage level of the clock and is  
not directly related to the transition time. The J and K inputs can change when  
the clock is in either state without affecting the flip-flop, provided that they are  
in the desired state during the recommended setup and hold times relative to  
DUAL JK NEGATIVE  
EDGE-TRIGGERED FLIP-FLOP  
FAST SCHOTTKY TTL  
thefalling edge of the clock. A LOW signal on S or C prevents clocking and  
D
D
forces Q or Q HIGH, respectively. Simultaneous LOW signals on S and C  
D
D
force both Q and Q HIGH.  
CONNECTION DIAGRAM  
J SUFFIX  
CERAMIC  
CASE 620-09  
V
C
C
CP  
K
J
S
Q
2
CC  
D1  
D2  
2
2
2
D2  
16  
15  
14  
13  
11  
10  
9
12  
16  
1
C
S
D
D
K
Q
Q
J
Q
Q
CP  
J
CP  
K
N SUFFIX  
S
C
D
D
PLASTIC  
CASE 648-08  
16  
5
1
CP  
2
3
4
6
7
8
1
GND  
K
J
S
Q
Q
Q
2
1
1
1
D1  
1
1
D SUFFIX  
SOIC  
CASE 751B-03  
FUNCTION TABLE (Each Half)  
Inputs  
16  
Output  
1
@ t  
@ t + 1  
n
n
J
K
Q
ORDERING INFORMATION  
L
L
L
H
L
Q
n
MC74FXXXJ  
Ceramic  
L
MC74FXXXN Plastic  
MC74FXXXD SOIC  
H
H
H
H
Q
n
Asynchronous Inputs:  
LOW Input to S sets Q to HIGH level  
D
LOGIC SYMBOL  
LOW Input to C sets Q to LOW level  
D
Clear and Set are independent of clock  
Simultaneous LOW on C and S makes both Q and Q HIGH  
4
10  
D
D
S
H = HIGH Voltage Level  
L = LOW Voltage Level  
S
D
D
J
J
3
1
2
Q
Q
5
Q
Q
11  
13  
9
t
t
= Bit time before clock pulse  
+ 1 = Bit time after clock pulse  
n
n
CP  
CP  
K
6
K
12  
7
C
D
15  
14  
V
= PIN 16  
CC  
GND = PIN 8  
FAST AND LS TTL DATA  
4-45  

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