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MC74ACT74D PDF预览

MC74ACT74D

更新时间: 2024-11-14 23:01:35
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 触发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
6页 192K
描述
DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP

MC74ACT74D 技术参数

是否Rohs认证: 不符合生命周期:Transferred
零件包装代码:SOIC包装说明:SOP, SOP14,.25
针数:14Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.03
Is Samacsys:N系列:ACT
JESD-30 代码:R-PDSO-G14JESD-609代码:e0
长度:8.65 mm负载电容(CL):50 pF
逻辑集成电路类型:D FLIP-FLOP最大频率@ Nom-Sup:125000000 Hz
最大I(ol):0.024 A位数:1
功能数量:2端子数量:14
最高工作温度:85 °C最低工作温度:-40 °C
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):240电源:5 V
传播延迟(tpd):11.5 ns认证状态:Not Qualified
座面最大高度:1.75 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30触发器类型:POSITIVE EDGE
宽度:3.9 mm最小 fmax:125 MHz
Base Number Matches:1

MC74ACT74D 数据手册

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DUAL D-TYPE POSITIVE  
EDGE-TRIGGERED  
FLIP-FLOP  
The MC74AC74/74ACT74 is a dual D-type flip-flop with Asynchronous Clear  
and Set inputs and complementary (Q,Q) outputs. Information at the input is  
transferred to the outputs on the positive edge of the clock pulse. Clock triggering  
occurs at a voltage level of the clock pulse and is not directly related to the transition  
time of the positive-going pulse. After the Clock Pulse input threshold voltage has  
been passed, the Data input is locked out and information present will not be  
transferred to the outputs until the next rising edge of the Clock Pulse input.  
Asynchronous Inputs:  
LOW input to S (Set) sets Q to HIGH level  
D
LOW input to C (Clear) sets Q to LOW level  
D
Clear and Set are independent of clock  
Simultaneous LOW on C and S makes both Q and Q HIGH  
D
D
N SUFFIX  
CASE 646-06  
PLASTIC  
Outputs Source/Sink 24 mA  
• ′ACT74 Has TTL Compatible Inputs  
V
C
D
CP  
S
Q
Q
2
CC  
14  
D2  
13  
2
2
D2  
10  
2
12  
11  
9
8
C
S
D1  
D2  
D
Q
CP  
Q
1
1
2
2
2
PIN NAMES  
CP  
Q
D
Q
S
C
1
1
2
D SUFFIX  
CASE 751A-03  
PLASTIC  
D1  
D2  
D , D  
Data Inputs  
1
2
CP , CP  
Clock Pulse Inputs  
Direct Clear Inputs  
Direct Set Inputs  
Outputs  
1
2
C
S
, C  
D1 D2  
1
2
3
CP  
4
5
6
7
, S  
D1 D2  
Q , Q , Q , Q  
C
D
S
Q
Q
1
GND  
1
1
2
2
D1  
1
1
D1  
1
LOGIC SYMBOL  
TRUTH TABLE (Each Half)  
Inputs  
CP  
Outputs  
Q
Q
1
1
S
C
D
Q
Q
S
C
D
D
D1  
D1  
D
CP  
1
1
L
H
L
H
H
H
H
L
L
X
X
X
X
X
X
H
L
H
L
H
H
L
L
H
H
L
H
H
H
H
L
X
Q
Q
0
0
Q
Q
2
CD  
2
S
D2  
H = HIGH Voltage Level  
L = LOW Voltage Level  
X = Immaterial  
2
D
CP  
2
2
= LOW-to-HIGH Clock Transition  
Q (Q ) = Previous Q(Q) before  
0
0
LOW-to-HIGH Transition of Clock  
FACT DATA  
5-1  

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