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MC74ACT377 PDF预览

MC74ACT377

更新时间: 2024-11-14 05:22:19
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 触发器时钟
页数 文件大小 规格书
6页 205K
描述
OCTAL D FLIP-FLOP WITH CLOCK ENABLE

MC74ACT377 数据手册

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OCTAL D  
FLIP-FLOP WITH  
CLOCK ENABLE  
The MC74AC377/74ACT377 has eight edge-triggered, D-type flip-flops with  
individual D inputs and Q outputs. The common buffered Clock (CP) input loads  
all flip-flops simultaneously, when the Clock Enable (CE) is LOW.  
The register is fully edge-triggered. The state of each D input, one setup time  
before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-  
flop’s Q output. The CE input must be stable only one setup time prior to the  
LOW-to-HIGH clock transition for predictable operation.  
Ideal for Addressable Register Applications  
Clock Enable for Address and Data Synchronization Applications  
Eight Edge-Triggered D Flip-Flops  
Buffered Common Clock  
Outputs Source/Sink 24 mA  
N SUFFIX  
CASE 738-03  
PLASTIC  
See MC74AC273 for Master Reset Version  
See MC74AC373 for Transparent Latch Version  
See MC74AC374 for 3-State Version  
• ′ACT377 Has TTL Compatible Inputs  
V
O
D
D
O
O
D
D
O
4
CP  
11  
CC  
7
7
6
6
5
5
4
DW SUFFIX  
CASE 751D-04  
PLASTIC  
20  
19  
18  
17  
16  
15  
14  
12  
13  
LOGIC SYMBOL  
1
2
3
4
5
6
7
9
8
10  
D
O
D
O
D
O
D
O
D
O
D
O
D
O
D
O
CE  
O
0
D
0
D
1
O
1
O
2
D
2
D
3
O
3
GND  
0
1
2
3
4
5
6
7
CP  
CE  
PIN NAMES  
0
1
2
3
4
5
6
7
D –D  
0
Data Inputs  
Clock Enable (Active LOW)  
Data Outputs  
7
CE  
Q –Q  
0
CP  
7
Clock Pulse Input  
MODE SELECT-FUNCTION TABLE  
Inputs  
Outputs  
Operating Mode  
CP  
CE  
L
D
Q
n
n
Load1′  
Load 0′  
H
H
L
L
L
H
H
X
X
No Change  
No Change  
Hold (Do Nothing)  
X
H = HIGH Voltage Level  
L = LOW Voltage Level  
X = Immaterial  
= LOW-to-HIGH Clock Transition  
FACT DATA  
5-1  

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