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MC74ACT377DWR2 PDF预览

MC74ACT377DWR2

更新时间: 2024-11-13 23:01:35
品牌 Logo 应用领域
安森美 - ONSEMI 触发器时钟
页数 文件大小 规格书
12页 115K
描述
Octal D Flip-Flop with Clock Enable

MC74ACT377DWR2 数据手册

 浏览型号MC74ACT377DWR2的Datasheet PDF文件第2页浏览型号MC74ACT377DWR2的Datasheet PDF文件第3页浏览型号MC74ACT377DWR2的Datasheet PDF文件第4页浏览型号MC74ACT377DWR2的Datasheet PDF文件第5页浏览型号MC74ACT377DWR2的Datasheet PDF文件第6页浏览型号MC74ACT377DWR2的Datasheet PDF文件第7页 
MC74AC377, MC74ACT377  
Octal D Flip-Flop with  
Clock Enable  
The MC74AC377/74ACT377 has eight edge-triggered, D-type  
flip-flops with individual D inputs and Q outputs. The common  
buffered Clock (CP) input loads all flip-flops simultaneously, when  
the Clock Enable (CE) is LOW. The register is fully edge-triggered.  
The state of each D input, one setup time before the LOW-to-HIGH  
clock transition, is transferred to the corresponding flip-flop’s Q  
output. The CE input must be stable only one setup time prior to the  
LOW-to-HIGH clock transition for predictable operation.  
http://onsemi.com  
PDIP–20  
N SUFFIX  
CASE 738  
20  
Ideal for Addressable Register Applications  
Clock Enable for Address and Data Synchronization Applications  
Eight Edge-Triggered D Flip-Flops  
1
SO–20  
DW SUFFIX  
CASE 751  
Buffered Common Clock  
20  
1
Outputs Source/Sink 24 mA  
See MC74AC273 for Master Reset Version  
See MC74AC373 for Transparent Latch Version  
See MC74AC374 for 3-State Version  
ACT377 Has TTL Compatible Inputs  
MSL = 1 for all Surface Mount  
TSSOP–20  
DT SUFFIX  
CASE 948E  
20  
1
EIAJ–20  
M SUFFIX  
CASE 967  
Chip Complexity: 292 FETS or 73 Gates  
20  
1
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 7 of this data sheet.  
DEVICE MARKING INFORMATION  
See general marking information in the device marking  
section on page 8 of this data sheet.  
Semiconductor Components Industries, LLC, 2001  
1
Publication Order Number:  
May, 2001 – Rev.6  
MC74AC377/D  

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